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研究生: 柯友加
You-chia Ker
論文名稱: 基於紅外光莫爾條紋對準光學模組開發
Development of Optical Alignment Module Based on Infrared Moiré Fringe
指導教授: 郭鴻飛
Hung-Fei Kuo
口試委員: 李佳翰
Jia-Han Li
徐勝均
Sheng-Dong Xu
學位類別: 碩士
Master
系所名稱: 工程學院 - 自動化及控制研究所
Graduate Institute of Automation and Control
論文出版年: 2022
畢業學年度: 110
語文別: 中文
論文頁數: 88
中文關鍵詞: 晶圓鍵合對位量測莫爾條紋紅外光影像拼接
外文關鍵詞: Moiré Fringe, Infrared Light
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  • 三維先進封裝可以透過層層堆疊擴展每個3D芯片的功能,遠遠超出傳統縮放的能力,然而進一步的尺寸小型化為半導體行業帶來了巨大的挑戰,其中在晶圓鍵合過程中對準量測技術為關鍵的製程步驟,在鍵合前能夠準確將晶圓精確對準能夠有效減少製程成本。在本篇論文中,利用紅外光能穿透矽晶圓的特性,提出適用於晶圓鍵合的紅外光學對位模組,並且製作出一種基於莫爾條紋的中心對稱光柵對準符號,能夠對兩片晶圓進行粗對準及細對準,進而量測出兩晶圓間的線性位移以及旋轉角位移,未來可回授偏移量於晶圓壓電載台進行晶圓鍵合前的校正補償。本文設計並實現可應用於晶圓鍵合的紅外光學對位模組之光路架構,並利用基於莫爾條紋的中心對稱光柵對準符號建構對位量測模組,為了達到對準的準確與即時性,使用一維線性擬合以及傅立葉轉換提取特定頻率方式濾波,分別對線性位移及旋轉角位移進行位移量預測,另外開發基於SURF特徵提取演算方法完成對準符號影像拼接,解決紅外光相機視野範圍不足的問題。實驗結果顯示此光學架構可偵測0.1°的最小精度角位移,量測誤差控制在±0.03°之內,角位移量計算時間約為0.2秒,以及可偵測0.5μm的最小精度線性位移,且量測誤差控制在±0.03μm之內,線性位移量計算時間約為0.04秒。


    Three-dimensional advanced packaging can expand the capabilities of each 3D chip through layer-by-layer stacking, however further size miniaturization has created enormous challenges for the semiconductor industry. Alignment is a key process step during wafer bonding technology, and accurate alignment of wafers before bonding can effectively reduce process costs. In this paper, the author proposed an infrared optical alignment module suitable for wafer bonding by utilizing the characteristic that infrared light can penetrate silicon wafers. Besides created a centrosymmetric grating alignment mark based on Moiré fringes, which can perform coarse alignment and fine alignment. This designed optical alignment module can detect the linear and angular displacement between two wafers. The author designs the setup of optical alignment used in wafer bonding system, and uses the center-symmetric grating based on Moiré fringes as the alignment mask of alignment module to predict overlay. In order to achieve the accuracy and immediacy of alignment, designing a filter which is based on one-dimensional linear fitting and Fourier transform. Besides develop image stitching algorithm based on SURF feature extraction. The experimental results show that this module can detect angular overlay of 0.1°, and the measurement error is controlled within ±0.03°,cost time 0.2 seconds;Linear overlay of 0.5μm, and the measurement error is controlled within ±0.03μm, cost time 0.04 seconds.

    目錄 致謝 I 摘要 II ABSTRACT III 目錄 IV 圖目錄 VI 表目錄 IX 第一章 緒論 1.1 前言 1.2 文獻探討 1.3 研究動機 1.4 論文架構 第二章 晶圓鍵合對準量測 2.1 簡介 2.2 先進封裝對準量測技術 2.3 紅外光對準量測參數 2.4 莫爾條紋線性、角位移量測模型 2.5 小結 第三章 紅外光對準量測設計 3.1 簡介 3.2 晶圓鍵合對準模組光學設計 3.3 對準符號設計與製作 3.4 對準量測 3.5 小結 第四章 紅外光影像處理 4.1 簡介 4.2 影像雜訊 4.3 完整對準符號影像拼接 4.4 即時對準符號影像演算 4.5小結 第五章 結論 5.1 分析與討論 5.2 研究貢獻 5.3 本文研究之未來方向 參考文獻

    [1] C. LÉCuyer, "Driving Semiconductor Innovation: Moore’s Law at Fairchild and Intel," Enterprise & Society, vol. 23, no. 1, pp. 133-163, 2022.
    [2] J. H. Lau, Semiconductor advanced packaging. Springer Nature, 2021.
    [3] H. Theuss, C. Geissler, and W. Hartner, "Trends in fan out wafer level packaging," in 2020 13th International Conference on Advanced Semiconductor Devices And Microsystems (ASDAM), 2020: IEEE, pp. 106-110.
    [4] J. H. Lau, "Recent advances and trends in advanced packaging," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 12, no. 2, pp. 228-252, 2022.
    [5] L Cao, TC Lee, R Chen, "Advanced Fanout Packaging Technology for Hybrid Substrate Integration," in 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022: IEEE, pp. 1362-1370.
    [6] S. L. Burkett, M. B. Jordan, R. P. Schmitt, L. A. Menk, and A. E. Hollowell, "Tutorial on forming through-silicon vias," Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films, vol. 38, no. 3, p. 031202, 2020.
    [7] B. Ding, Z.-H. Zhang, L. Gong, M.-H. Xu, and Z.-Q. Huang, "A novel thermal management scheme for 3D-IC chips with multi-cores and high power density," Applied thermal engineering, vol. 168, p. 114832, 2020.
    [8] J. H. Lau, "3D IC Integration and 3D IC Packaging," in Semiconductor Advanced Packaging: Springer, 2021, pp. 343-378.
    [9] JH Lau, CT Ko, KM Yang, "Panel-level fan-out RDL-first packaging for heterogeneous integration," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 7, pp. 1125-1137, 2020.
    [10] J. Chang, J. Lu, and B. Ali, "Advanced Outlier Die Control Technology in Fan-Out Panel Level Packaging Using Feedforward Lithography," in 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021: IEEE, pp. 72-77.
    [11] F. C. Ng and M. A. Abas, "Underfill flow in flip-chip encapsulation process: a review," Journal of Electronic Packaging, vol. 144, no. 1, 2022.
    [12] H Park, J Park, S Kim, "Deep reinforcement learning-based optimal decoupling capacitor design method for silicon interposer-based 2.5-D/3-D ICs," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 10, no. 3, pp. 467-478, 2020.
    [13] J. H. Lau, "2.5 D IC Integration," in Semiconductor Advanced Packaging: Springer, 2021, pp. 299-342.
    [14] PK Huang, CY Lu, WH Wei, "Wafer level system integration of the fifth generation CoWoS®-S with high performance Si interposer at 2500 mm2," in 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021: IEEE, pp. 101-104.
    [15] ML Lin, MS Liu, HW Chen, "Organic Interposer CoWoS-R+(plus) Technology," in 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022: IEEE, pp. 1-6.
    [16] R. Agarwal, P. Cheng; P. Shah, "3D Packaging for Heterogeneous Integration," in 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), 2022: IEEE, pp. 1103-1107.
    [17] L. Sun, M.-h. Chen, L. Zhang, P. He, and L.-s. Xie, "Recent progress in SLID bonding in novel 3D-IC technologies," Journal of Alloys and Compounds, vol. 818, p. 152825, 2020.
    [18] R Silver, T Germer, R Attota, "Fundamental limits of optical critical dimension metrology: a simulation study," in Metrology, Inspection, and Process Control for Microlithography XXI, 2007, vol. 6518: SPIE, pp. 290-306.
    [19] J. H. Lau, "Evolution, challenge, and outlook of TSV, 3D IC integration and 3D silicon integration," in 2011 International symposium on advanced packaging materials (APM), 2011: IEEE, pp. 462-488.
    [20] C. Ageorges, L. Ye, and M. Hou, "Advances in fusion bonding techniques for joining thermoplastic matrix composites: a review," Composites Part A: applied science and manufacturing, vol. 32, no. 6, pp. 839-857, 2001.
    [21] Y.-T. Cheng, L. Lin, and K. Najafi, "Localized silicon fusion and eutectic bonding for MEMS fabrication and packaging," Journal of microelectromechanical systems, vol. 9, no. 1, pp. 3-8, 2000.
    [22] L Di Cioccio, F Baudin, P Gergaud, "Modeling and integration phenomena of metal-metal direct bonding technology," ECS Transactions, vol. 64, no. 5, p. 339, 2014.
    [23] G Gao, L Mirkarimi, T Workman, "Low temperature Cu interconnect with chip to wafer hybrid bonding," in 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019: IEEE, pp. 628-635.
    [24] V. Dragoi and P. Lindner, "Chapter 34 - Wafer-Bonding Equipment," in Handbook of Silicon Based MEMS Materials and Technologies (Second Edition), M. Tilli, T. Motooka, V.-M. Airaksinen, S. Franssila, M. Paulasto-Kröckel, and V. Lindroos Eds. Boston: William Andrew Publishing, 2015, pp. 648-663.
    [25] M. Shrivastava and V. Ramgopal Rao, "A roadmap for disruptive applications and heterogeneous integration using two-dimensional materials: State-of-the-art and technological challenges," Nano Letters, vol. 21, no. 15, pp. 6359-6381, 2021.
    [26] J. Zhu, S. Hu, J. Yu, and Y. Tang, "Alignment method based on matched dual-grating moiré fringe for proximity lithography," Optical Engineering, vol. 51, no. 11, p. 113603, 2012.
    [27] D. P. Sanders, "Advances in patterning materials for 193 nm immersion lithography," Chemical reviews, vol. 110, no. 1, pp. 321-360, 2010.
    [28] L. Di Cioccio, I. Radu, P. Gueguen, and M. Sadaka, "Direct bonding for wafer level 3D integration," in 2010 IEEE International Conference on Integrated Circuit Design and Technology, 2010: IEEE, pp. 110-113.
    [29] B. Kim, T. Matthias, M. Wimplinger, and P. Lindner, "Advanced wafer bonding solutions for TSV integration with thin wafers," in 2009 IEEE International Conference on 3D System Integration, 2009: IEEE, pp. 1-6.
    [30] M. Kondo, R. Komiyama, H. Miyashita, and S. S. Lee, "Local tentative bonding method to maintain alignment accuracy in bonding process using resin as an adhesive material," The Journal of Engineering, vol. 2018, no. 5, pp. 274-278, 2018.
    [31] J De Vos, L Peng, "Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects," in 2016 IEEE International 3D Systems Integration Conference (3DIC), 2016: IEEE, pp. 1-5.
    [32] L Peng, SW Kim, S Iacovo ,"Advances in sicn-sicn bonding with high accuracy wafer-to-wafer (w2w) stacking technology," in 2018 IEEE International Interconnect Technology Conference (IITC), 2018: IEEE, pp. 179-181.
    [33] X. Qi, H. Yan, S. Zhou, Q. Kang, and C. Wang, "Moiré-Based Nanoprecision Bonding Alignment System for Hybrid Integration," in 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA), 2021: IEEE, pp. 24-26.
    [34] T. Huesgen, G. Lenk, B. Albrecht, P. Vulto, T. Lemke, and P. Woias, "Optimization and characterization of wafer-level adhesive bonding with patterned dry-film photoresist for 3D MEMS integration," Sensors and Actuators A: Physical, vol. 162, no. 1, pp. 137-144, 2010/07/01/ 2010
    [35] H. T. Hsu, W. S. Su, C. C. Lee, H. Y. Huang, H. Y. Lin, and W. Fang, "3D integration of micro optical components on flexible transparent substrate with through-hole- vias," in 2010 IEEE 23rd International Conference on Micro Electro Mechanical Systems (MEMS), 24-28 Jan. 2010 2010, pp. 536-539, doi: 10.1109/MEMSYS.2010.5442446.
    [36] H. S. Yang and M. S. Bakir, "3D integration of CMOS and MEMS using mechanically flexible interconnects (MFI) and through silicon vias (TSV)," in 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 1-4 June 2010 2010, pp. 822-828, doi: 10.1109/ECTC.2010.5490716.
    [37] J. U. Knickerbocker et al., "3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias," IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1718-1725, 2006, doi: 10.1109/JSSC.2006.877252.
    [38] I. Sugaya, H. Mitsuishi, H. Maeda, M. Okada, and K. Okamoto, "High precision alignment process for future 3D wafer bonding," in 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), 26-29 May 2015 2015, pp. 348-353, doi: 10.1109/ECTC.2015.7159616.
    [39] S. Farrens, "Vertical Integration: A Confederacy of Alignment, Bonding, and Materials Technologies," MRS Proceedings, vol. 970, pp. 0970-Y04-05, 2006, Art no. 0970-y04-05, doi: 10.1557/PROC-0970-Y04-05.
    [40] S. Farrens, "Wafer and Die Bonding Technologies for 3D Integration," vol. 1112, 01/01 2008, doi: 10.1557/PROC-1112-E01-06.
    [41] F Kurz, T Plach, J Süss, "High precision low temperature direct wafer bonding technology for wafer-level 3D ICs manufacturing," ECS Transactions, vol. 75, no. 9, p. 345, 2016.
    [42] P. H. Marc and S. M. Douglas, "Overview of SWIR detectors, cameras, and applications," in Proc.SPIE, 2008, vol. 6939, doi: 10.1117/12.777776.
    [43] M. Tara, B. Robert, D. Peter, G. Mari-Anne, and S. Tom, "640x512 InGaAs focal plane array camera for visible and SWIR imaging," in Proc.SPIE, 2005, vol. 5783, doi: 10.1117/12.603406.
    [44] J Benschop, A Engelen, H Cramer, "Integrated scatterometry for tight overlay and CD control to enable 20-nm node wafer manufacturing," in Proc.SPIE, 2013, vol. 8683, doi: 10.1117/12.2011507.
    [45] H Lee, B Lee, S Han, "Overlay accuracy investigation for advanced memory device," in Proc.SPIE, 2015, vol. 9424, doi: 10.1117/12.2085270.
    [46] B. J. Kim, J. S. Song, J. T. Kim, J. H. Jo, S. Chang, and K. C. Yuk, "Determination of small angular displacement by moiré fringes of matched radial–parallel gratings," Appl. Opt., vol. 36, no. 13, pp. 2848-2855, 1997/05/01 1997, doi: 10.1364/AO.36.002848.
    [47] J. Shao, Y. Ding, H. Tian, X. Li, X. Li, and H. Liu, "Digital moiré fringe measurement method for alignment in imprint lithography," Optics & Laser Technology, vol. 44, no. 2, pp. 446-451, 2012/03/01/ 2012, doi: https://doi.org/10.1016/j.optlastec.2011.08.010.
    [48] H. F. Kuo and Frederick, "Gaussian beam incident on the one-dimensional diffraction gratings with the high-K metal gate stack structures," (in eng), J Nanosci Nanotechnol, vol. 14, no. 4, pp. 2780-5, Apr 2014, doi: 10.1166/jnn.2014.8588.
    [49] S. H. Kong, D. D. L. Wijngaards, and R. F. Wolffenbuttel, "Infrared micro-spectrometer based on a diffraction grating," Sensors and Actuators A: Physical, vol. 92, no. 1, pp. 88-95, 2001/08/01/ 2001, doi: https://doi.org/10.1016/S0924-4247(01)00544-1.
    [50] A. W. Lohmann and D. E. Silva, "An interferometer based on the Talbot effect," Optics Communications, vol. 2, no. 9, pp. 413-415, 1971/02/01/ 1971, doi: https://doi.org/10.1016/0030-4018(71)90055-1.
    [51] B. Pain, T. Cunningham, B. Hancock, C. Wrigley, and C. Sun, "Excess noise and dark current mechanisms in CMOS imagers," in IEEE Workshop on CCD’s and Advanced Image Sensors, Karuizawa, Nagano, Japan, 2005.
    [52] F. Luisier, T. Blu, and M. Unser, "Image Denoising in Mixed Poisson–Gaussian Noise," IEEE Transactions on Image Processing, vol. 20, no. 3, pp. 696-708, 2011, doi: 10.1109/TIP.2010.2073477.
    [53] R. H. Chan, H. Chung-Wa, and M. Nikolova, "Salt-and-pepper noise removal by median-type noise detectors and detail-preserving regularization," IEEE Transactions on Image Processing, vol. 14, no. 10, pp. 1479-1485, 2005, doi: 10.1109/TIP.2005.852196.
    [54] A. Maity, A. Pattanaik, S. Sagnika, and S. Pani, "A Comparative Study on Approaches to Speckle Noise Reduction in Images," in 2015 International Conference on Computational Intelligence and Networks, 12-13 Jan. 2015 2015, pp. 148-155, doi: 10.1109/CINE.2015.36.
    [55] M. Brown and D. G. Lowe, "Automatic Panoramic Image Stitching using Invariant Features," International Journal of Computer Vision, vol. 74, no. 1, pp. 59-73, 2007/08/01 2007, doi: 10.1007/s11263-006-0002-3.
    [56] D. G. Lowe, "Object recognition from local scale-invariant features," in Proceedings of the Seventh IEEE International Conference on Computer Vision, 20-27 Sept. 1999 1999, vol. 2, pp. 1150-1157 vol.2, doi: 10.1109/ICCV.1999.790410.
    [57] A. Li, W. Jiang, W. Yuan, D. Dai, S. Zhang, and Z. Wei, "An Improved FAST+SURF Fast Matching Algorithm," Procedia Computer Science, vol. 107, pp. 306-312, 2017/01/01/ 2017, doi: https://doi.org/10.1016/j.procs.2017.03.110.
    [58] M. A. Fischler and R. C. Bolles, "Random sample consensus: a paradigm for model fitting with applications to image analysis and automated cartography," Commun. ACM, vol. 24, no. 6, pp. 381–395, 1981, doi: 10.1145/358669.358692.
    [59] J. Kim, "New wafer alignment process using multiple vision method for industrial manufacturing," Electronics, vol. 7, no. 3, p. 39, 2018.

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