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研究生: 陳昱豪
Yu-Hau Chen
論文名稱: 基於FPGA嵌入式平台之影像量測系統開發
Development of an Image-Based Measurement System Using FPGA Embedded Platform
指導教授: 林紀穎
Chi-Ying Lin
口試委員: 謝宏麟
Hung-Lin Hsieh
黃育熙
Yu-Hsi Huang
學位類別: 碩士
Master
系所名稱: 工程學院 - 機械工程系
Department of Mechanical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 120
中文關鍵詞: 現場可編程邏輯閘陣列翹曲量量測影像式量測系統疊紋法
外文關鍵詞: warpage measurement, Image-based measurement system, method
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影像式自動化量測系統因具備非接觸式、高解析度的優點,近年來被廣泛應用於微小元件量測。然而現有影像式量測系統普遍受限於電腦影像資料處理運算速度,其量測範圍與實際應用亦因此大幅受限,為此本研究提出一套在FPGA架構中實現高可調性之影像式精密量測系統,並以微小角度、微距量測與物體形貌重建量測實驗驗證本系統性能。
本系統以Camera Link 介面VC-4MC-M180相機工業相機擷取影像,並結合Moiré演算法與掃描式輪廓技術重建出晶圓形貌。開發系統使用的硬體與軟體主要分別為Xilinx Virtex-5 SX95T晶片的NI FPGA 7966R、影像擷取卡NI 1483與Labview FPGA。為了提升系統效能,本研究藉由對2048×2048解析度影像擷取感興趣區域做影像處理與疊紋分析運算,實現幀率157.1 fps之高速且即時晶圓曲率量測系統。實驗結果顯示於處理影像幀率為39.6 fps下,本系統有效量測晶圓曲率變化量可達3100 μrad、有效量測變化量之頻率達1.9 Hz與晶圓曲率量測解析度約為4 μrad,相較於PC架構量測系統之量測結果,本系統量測效能大幅優於PC架構。此外本研究亦分析各演算法所消耗的FPGA邏輯單元使用情況,以利未來實現於低成本之量測系統開發。


Image-based automatic inspection systems have the advantages of non-contact measurement and high resolution. However, the effective measurement range and performance are also greatly limited by the computational efficiency in most available computer systems. This thesis presents a FPGA-based precision measurement system and justifies its system performance with several tests including micro-angle variation measurement, distance measurement, and object surface reconstruction.
To achieve high speed and real-time wafer warpage measurement, this study implemented image processing and moiré algorithms on a large region of interest in which its maximum processing speed could be up to 157.1 fps with a 2048 × 2048 image resolution. The measured results of this FPGA-based system are justified using the ones measured by high precision commercial instruments. The experimental results demonstrate that at a 39.6 fps image frame rate the effective warpage measurement range could be up to 3100 μrad with a 1.9 Hz maximum measurement variation frequency and a 4 μrad resolution. Compared to the results obtained from a PC based image measurement system, the performance of our developed FPGA-based measurement system has been significantly improved. Moreover, the analysis of the used FPGA logic units is also presented for more effectively-streamlined commercial developments in the future.

摘要 III ABSTRACT IV 誌謝 V 目錄 圖表索引 III 符號索引 7 第一章 緒言 8 1.1 研究背景 8 1.2 文獻回顧 9 1.2.1 PC-based之影像量測系統 9 1.2.2 GPU影像量測系統 11 1.2.3 FPGA-based之影像量測系統 12 1.3 研究動機與目的 14 1.4 論文架構 15 第二章 FPGA硬體架構 16 2.1 可規劃邏輯元件分類 16 2.1.1 可程式化邏輯陣列 16 2.1.2 可程式化陣列邏輯 17 2.1.3 可程式化唯讀記憶體 17 2.1.4 可程式化邏輯裝置 17 2.1.5 複合式可程式邏輯裝置 18 2.2 XILLINX FPGA之基本架構 18 2.2.1 可組態邏輯區塊 20 2.2.2 輸入輸出區塊 21 2.2.3 塊狀記憶體 22 2.2.4 二進位乘法器 23 2.2.5 數位時鐘管理器 24 2.2.6 階層式連接結構 26 2.3 硬體約束議題討論 27 2.3.1 定點數分析 27 2.3.2 PCI匯流排 29 2.3.3 First input first output 29 2.3.4 DMA技術 31 第三章 應用量測原理與FPGA設計流程 33 3.1 應用量測原理 33 3.1.1 疊紋形貌描述 35 3.1.2 疊紋形態變化之疊紋橫移原理 42 3.1.3 亞條紋移相分析原理 44 3.1.4 解相位纏繞原理 46 3.1.5 自動準直儀量測原理 51 3.1.6 疊紋相位變化與待測平面傾斜角度關係 52 3.1.7 掃描式輪廓重建技術 54 3.1.8 小結 56 3.2 問題描述與系統建立 57 3.3 CAMERA LINK 介面及圖相數據介面訊號 58 3.3.1 VC-4MC-M180相機規格 59 3.3.2 Camera Link技術 59 3.3.3 Camera Link之相機訊號 60 3.3.4 埠配置 62 3.4 系統設計流程 65 3.4.1 系統架構 65 3.4.2 軟體流程 69 3.4.3 感興趣區域演算法 70 3.4.4 二值化 72 3.4.5 數位式影像交疊 73 3.4.6 CORDIC演算法 76 3.4.7 相位展開演算法 77 3.5 FPGA資源分析 79 3.5.1 低資料流資源分析 79 3.5.2 高資料流資源分析 81 第四章 系統性能驗證與討論 82 4.1 系統角度量測校正 82 4.1.1 系統角度量測校正架構 82 4.1.2 系統角度量測校正結果 83 4.2 晶圓量測實驗 85 4.2.1 晶圓表面曲率驗證 85 4.2.2 FPGA晶圓曲率量測系統 87 4.2.3 動態晶圓量測結果 88 4.3 系統角度量測校能驗證 89 4.3.1 最小解析度量測範圍 89 4.3.2 最大解析度量測範圍 92 4.3.3 速度極限量測範圍 97 4.3.4系統重覆性量測 102 4.3.5 系統穩定度量測 104 4.4 系統微距量測校能驗證 105 4.5 基於FPGA之高資料流與低資料流與基於PC系統效能比較 106 第五章 結論與未來展望 108 5.1 結論 108 5.2 本研究貢獻 108 5.3 未來展望 109 參考文獻 110

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