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研究生: 奉啓元
Chi-Yuan Feng
論文名稱: 三相四階飛馳電容升壓型功率因數修正器設計與研製
Design and Implementation of a Three-phase Four-level Flying Capacitor Power Factor Correction
指導教授: 邱煌仁
Huang-Jen Chiu
口試委員: 邱煌仁
Huang-Jen Chiu
張佑丞
Yu-Cheng Chang
劉宇晨
Yu-Chen Liu
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2022
畢業學年度: 110
語文別: 中文
論文頁數: 85
中文關鍵詞: 動態相移脈寬調變法多階式飛馳電容功率因數修正器鎖相迴路
外文關鍵詞: Dynamic Phase Shift PWM Modulation Method, phase Four-level Flying-capacitor Power Factor Corrector, Phase-locked Loop
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  • 目錄 摘要 i Abstract ii 致謝 iii 目錄 v 圖索引 vii 表索引 x 第一章 緒論 1 1.1 研究動機與目的 1 1.2 章節大綱 3 第二章 三相功率因數修正器 4 2.1 四階式飛馳電容升壓型轉換器 4 2.2 動作原理 5 2.3 三相調變法 10 2.3.1 空間向量脈波寬度調變(SVPWM) 11 2.3.2 載波脈寬調變法(CBPWM) 19 2.3.3 動態相移脈寬調變法(DPSPWM) 24 第三章 功率元件設計 30 3.1 電感設計 30 3.2 開關設計 38 3.3 輸出電容及箝位電容設計 42 第四章 鎖相迴路設計 44 4.1 派克轉換 44 4.2 鎖相迴路介紹 44 4.2.1 單同步參考坐標系鎖相迴路(SSRF-PLL) 45 4.2.2 雙同步參考軸鎖相迴路(DDSRF-PLL) 47 4.2.3 雙二階廣義積分器鎖相迴路(DSOGI-PLL) 52 4.2.4 三相不平衡鎖相迴路適應性分析 55 第五章 電路模擬與實驗結果 60 5.1 模擬結果 60 5.1.1 模擬電路圖 60 5.1.2 模擬波形 61 5.2 實驗結果 62 5.2.1 實際電路圖 63 5.2.2 實驗波形 63 5.2.3 實驗數據 66 第六章 結論與未來展望 68 6.1 結論 68 6.2 未來展望 69 參考文獻 70

    [1] M. D. Manjrekar, R. Kieferndorf and G. Venkataramanan, "Power electronic transformers for utility applications," Conference Record of the 2000 IEEE Industry Applications Conference. Thirty-Fifth IAS Annual Meeting and World Conference on Industrial Applications of Electrical Energy (Cat. No.00CH37129), 2000, pp. 2496-2502
    [2] Infineon Technologies, CoolSiC™ 1200 V SiC MOSFET Application Note,https://www.infineon.com/dgdl/Infineon-CoolSiC_MOSFET_1200V-SiC_trench_power_device-ApplicationNotes-v01_01-EN.pdf?fileId=5546d462617643590161c27fbcda0aae
    [3] Abraham I. Pressman, Keith Billings, Taylor Morey,交換式電源設計,呂文隆、張簡士琨、曾國境譯,第三版,全華圖書股份有限公司,2012年。
    [4] "IEEE Recommended Practice and Requirements for Harmonic Control in Electric Power Systems," in IEEE Std 519-2014 (Revision of IEEE Std 519-1992) , vol., no., pp.1-29, 11 June 2014.
    [5] EUROPEAN POWER SUPPLY MANUFACTURERS ASSOCIATION,https://emcfastpass.com/wpcontent/uploads/2017/04/Applicability_flow_chart.pdf
    [6] 徐永隆,具動態載波相移脈寬調變之三相六階飛馳電容功率因數修正器,國立臺灣科技大學電子工程系博士論文,2021年。
    [7] Y. -L. Syu, Z. Liao, N. -T. Fu, Y. -C. Liu, H. -J. Chiu and R. C. N. Pilawa-Podgurski, "Design and Control of A High Power Density Three-Phase Flying Capacitor Multilevel Power Factor Correction Rectifier," 2021 IEEE Applied Power Electronics Conference and Exposition (APEC), 2021, pp. 613-618.
    [8] B. P. McGrath and D. G. Holmes, "Enhanced voltage balancing of a flying capacitor multilevel converter using Phase Disposition (PD) modulation," 2009 IEEE Energy Conversion Congress and Exposition, 2009, pp. 3108-3115.
    [9] M. Khazraei, H. Sepahvand, K. Corzine and M. Ferdowsi, "A generalized capacitor voltage balancing scheme for flying capacitor multilevel converters," 2010 Twenty-Fifth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 2010, pp. 58-62.
    [10] Ó. López et al., "Carrier-Based PWM Equivalent to Multilevel Multiphase Space Vector PWM Techniques," in IEEE Transactions on Industrial Electronics, vol. 67, no. 7, pp. 5220-5231, July 2020.
    [11] Yo-Han Lee, Dong-Hyun Kim and Dong-Seok Hyun, "Carrier based SVPWM method for multi-level system with reduced HDF [harmonic distortion factor]," Conference Record of the 2000 IEEE Industry Applications Conference. Thirty-Fifth IAS Annual Meeting and World Conference on Industrial Applications of Electrical Energy (Cat. No.00CH37129), 2000, pp. 1996-2003 vol.3.
    [12] Q. Yan, X. Zhang, T. Zhao, X. Yuan and R. Zhao, "An Analytical Simplified Three-Level SVPWM With Unified Zero-Sequence Component Injection," in IEEE Transactions on Power Delivery, vol. 37, no. 3, pp. 2417-2420, June 2022.
    [13] J. Sabarad and G. H. Kulkarni, "Comparative analysis of SVPWM and SPWM techniques for multilevel inverter," 2015 International Conference on Power and Advanced Control Engineering (ICPACE), 2015, pp. 232-237.
    [14] TIDA-00779, "230 V, 3.5 kW PFC With >98% Efficiency, Optimized for BOM and Size Reference Design," Texas Instruments Designs, January 2016.
    [15] R. Hou, J. Lu and D. Chen, "Parasitic capacitance Eqoss loss mechanism, calculation, and measurement in hard-switching for GaN HEMTs," 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), 2018, pp. 919-924.
    [16] S. Ali, I. Setiawan and S. Handoko, "Design and Performance Test of Three Phased Synchronous Reference Frame-Phase Locked Loop (SRF-PLL) using DSPIC30F4011," 2018 5th International Conference on Information Technology, Computer, and Electrical Engineering (ICITACEE), 2018, pp. 51-56.
    [17] X. Wu, T. Huang, X. Chen, H. Hu and G. He, "Frequency Characteristic and Impedance Analysis on Three-Phase Grid-Connected Inverters Based on DDSRF-PLL," 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia), 2019, pp. 1053-1058.
    [18] R. A. Flores, I. Y. H. Gu and M. H. J. Bollen, "Positive and negative sequence estimation for unbalanced voltage dips," 2003 IEEE Power Engineering Society General Meeting (IEEE Cat. No.03CH37491), 2003, pp. 2498-2502.
    [19] J. Li-Jun et al., "Unbalanced control of grid-side converter based on DSOGI-PLL," 2015 IEEE 10th Conference on Industrial Electronics and Applications (ICIEA), 2015, pp. 1145-1149.
    [20] X. Wang, "Optimization strategy of DSOGI-PLL precision under harmonic interference conditions," 2020 IEEE Sustainable Power and Energy Conference (iSPEC), 2020, pp. 852-857

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