本論文主旨在探討蛇狀延遲線在高速數位電路印刷電路板中之信號完整性效應。由於其結構主要的雜訊來源是傳輸線間的串音雜訊，因此本論文將針對其幾何結構尺寸為參數來設計其接收端梯階串音雜訊的設計圖表，並針對不同速度的輸入信號與幾何結構參數來進行串音雜訊的模擬，探討其相關參數對於該結構下對於串音雜訊大小的影響效應，最後利用時域與頻域下的實驗結果來針對模擬與理論的部分驗證。另外，對於針對幾種業界常見的非矩形佈線結構之蛇狀延遲線進行模擬分析，藉以了解業界高速數位電路板中真實佈線結構的蛇狀延遲線之實務設計準則；由結果得到以TDR來看Type8有較佳的抗雜訊能力，在TDT來看Type7有較佳的表現，可以透過內層走線有效降低遠端串因雜訊，改善在TDR的缺點。提供業界相關工程師於蛇狀延遲線佈線設計時，能有效避開因串音現象所產生的信號完整性問題。

The motif of this thesis is to research the application of serpentine delay line on printed circuit board. The major noise comes from crosstalk between transmission lines, so this thesis will be based on geometry construction dimension parameter to design the laddering wave of receiver, such as change input signal source wave and structure to simulation in frequency domain and time domain. The field test and measurement were performed to confirm the simulation. Through theory analysis the major influence factors of crosstalk were discussed. We also simulate and analyze popular serpentine delay line which were adopted by industries frequently, and verify the physical performances. The influence of different serpentine delay line of crosstalk for signal integrity was analyzed quantitatively. We provide an effective design technique
and algorithm to keep away problem caused from crosstalk phenomenon.

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