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研究生： 王冠崴
Kuan-Wei Wang
論文名稱： 基於IEEE 802.15.4a/z之脈衝超寬頻發送器實現與時序同步電路設計
Design and Implementation of an IR-UWB Transmitter and Timing Synchronization Circuit based on IEEE 802.15.4a/z
指導教授： 沈中安
Chung-An Shen
口試委員: 吳晉賢
Chin-Hsien Wu
黃琴雅
Chin-Ya Huang
陳永耀
Yung-Yao Chen
沈中安
Chung-An Shen
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 89
中文關鍵詞： IEEE 802.15.4a/z 、HRP UWB PHY 、數位基頻 、IR-UWB發送器 、時序同步電路 、FPGA
外文關鍵詞： IEEE 802.15.4a/z, HRP UWB PHY, Digital baseband, IR-UWB Transmitter, Timing Synchronization, FPGA
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  •  上一筆

    • 脈衝超寬頻(Impulse-Radio UWB)通訊是一種使用脈衝訊號進行短距離無線訊號傳輸的技術，除了進行數據傳輸外，也因為其奈秒(ns)等級的脈衝訊號特性，可以進行精準的測距以及定位，讓這項技術可以應用在許多新興領域，如免持鑰匙、智慧家庭以及各種物聯網應用。而脈衝超寬頻通訊在電路實現上有許多困難，如電路的高運作頻率、大頻寬的資料量以及高設計複雜度的規格...等。因此，在本論文中將設計與實現一個基於IEEE 802.15.4a/z HRP UWB PHY的數位基頻發送器與接收端的時序同步(Timing Synchronization)電路。整體電路會使用平行化的電路設計技巧來克服實現的困難，並且針對IEEE 802.15.4a/z標準進行分析，找出設計的瓶頸並優化高複雜度的電路，進行模組分工並根據特殊功能需求進行優化。本論文所提出的設計將會實現在Xilinx ZC706 FPGA中並結合MATLAB環境進行完整規格與功能驗證。

    Impulse-Radio ultrawideband (IR-UWB) communication technology is a short-range wireless signal transmission technique that utilizes impulse signals for communication. In addition to data transmission, it is capable of precise ranging and localization due to its nanosecond-level pulse signal characteristics. This makes it applicable in emerging fields such as keyless entry systems, smart homes, and the Internet of Things (IoT). However, implementing IR-UWB communication faces challenges such as high operating frequencies, large bandwidth data, and complex design requirements. Therefore, this paper aims to design and implement a digital baseband transmitter and a timing synchronization circuit for receiver based on the IEEE 802.15.4a/z HRP UWB PHY. The overall circuit utilizes parallelization techniques to overcome implementation challenges and optimizes high-complexity circuits by analyzing the IEEE 802.15.4a/z standard, identifying design bottlenecks, and optimizing modules based on specific functional requirements. The proposed design will be implemented on the Xilinx ZC706 FPGA platform and validated using MATLAB environment for comprehensive specification and functional verification.

    Abstract in Chinese . . . . . . . . . . . . . . . . . . . . . . . . . . iii Abstract in English . . . . . . . . . . . . . . . . . . . . . . . . . . iv Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 IEEE 802.15.4a/z HRP UWB PHY . . . . . . . . . . . . . 6 2.1.1 Operation Modes of HRP UWB PHY . . . . . . . 8 2.1.2 Packet Format of HRP UWB PHY . . . . . . . . . 9 2.1.3 Modulations of HRP UWB PHY . . . . . . . . . . 16 2.2 Timing Synchronization . . . . . . . . . . . . . . . . . . 20 2.2.1 Concepts of Timing Synchronization . . . . . . . 20 2.2.2 Related Work . . . . . . . . . . . . . . . . . . . . 21 3 Proposed Transmitter Architecture . . . . . . . . . . . . . . . . 24 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 PPDU Data Generator . . . . . . . . . . . . . . . . . . . . 25 3.2.1 PHR Generator and SECDED Encoder . . . . . . 26 3.2.2 Reed Solomon Encoder . . . . . . . . . . . . . . . 27 3.2.3 Bit Ordering Unit . . . . . . . . . . . . . . . . . . 29 3.3 Convolutional Encoder . . . . . . . . . . . . . . . . . . . 31 3.4 Symbol Mapper . . . . . . . . . . . . . . . . . . . . . . . 32 3.5 SHR Generator . . . . . . . . . . . . . . . . . . . . . . . 37 3.6 STS Generator . . . . . . . . . . . . . . . . . . . . . . . 39 3.7 TX PHY Integration . . . . . . . . . . . . . . . . . . . . 40 3.7.1 Controller and FSM . . . . . . . . . . . . . . . . 41 3.7.2 TX PHY Interface . . . . . . . . . . . . . . . . . 44 4 Proposed IR-UWB Timing Synchronization Circuit . . . . . . . 45 4.1 Timing Synchronization Algorithm . . . . . . . . . . . . . 46 4.1.1 Correlation Calculation . . . . . . . . . . . . . . . 46 4.1.2 2-stage Synchronization Method . . . . . . . . . . 50 4.2 Timing Synchronization Architecture . . . . . . . . . . . 52 4.2.1 Sample Buffer . . . . . . . . . . . . . . . . . . . 53 4.2.2 Data Multiplexing Unit . . . . . . . . . . . . . . . 54 4.2.3 SYNC Correlation Unit . . . . . . . . . . . . . . . 55 4.2.4 2-stage Synchronization Unit . . . . . . . . . . . . 59 4.2.5 Sample Alignment Unit . . . . . . . . . . . . . . 61 5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 62 5.1 UWB Transmitter Results . . . . . . . . . . . . . . . . . . 62 5.1.1 Environment Setup . . . . . . . . . . . . . . . . . 62 5.1.2 Implementation Results . . . . . . . . . . . . . . 63 5.2 Time Synchronization Results . . . . . . . . . . . . . . . 66 5.2.1 Implementation Results . . . . . . . . . . . . . . 67 6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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    全文公開日期 2028/07/24 (國家圖書館：臺灣博碩士論文系統)
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