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研究生: 楊雁行
Yan-hang Yang
論文名稱: 快速熱退火對多通道複晶矽薄膜電晶體特性改善之研究
Investigation on the Performance Improvement of Multi-Channel Poly-Si TFT with Rapid Thermal Annealing
指導教授: 范慶麟
Ching-lin Fan
口試委員: 李志堅
Chih-chien Lee
王錫九
Shea-jue Wang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2007
畢業學年度: 95
語文別: 中文
論文頁數: 73
中文關鍵詞: 複晶矽薄膜電晶體快速熱退火閘極氧化層多通道
外文關鍵詞: poly-si TFT, rapid thermal annealing, gate oxide thickness, multi-channel
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  • 本論文中分為兩個部份,第一個部份我們利用本實驗室自行架設的中空陰極化學氣相沉積(Hollow Cathode Chemical Vapor Deposition)系統,在低溫下沉積薄膜,找出最佳製程參數,並分析薄膜特性。
    第二部份我們探討快速熱退火(Rapid Thermal Annealing;RTA)對不同厚度的閘極氧化層以及多重通道(multi-channel)結構處理後特性改善的研究。實驗結果顯示對於經過RTA處理後且閘極氧化層厚度越薄的薄膜電晶體,其電性改善的幅度越多。這是因為快速熱退火的高溫可以增加薄膜的品質,減少薄膜內的缺陷進而改善元件特性。
    此外,我們也進行有關多重通道複晶矽薄膜電晶體的研究。藉由增加多通道的數目,可以改善元件的電特性,像是降低臨界電壓(threshold voltage)及次臨界擺幅(subthreshold voltage),甚至可以抑制當閘極通道長度(gate length)越短時所產生的短通道效應(short channel effect)。


    This thesis is divided into two parts. The first part, we can use Hollow Cathode Chemical Vapor Deposition System which is established by our laboratory to deposit oxide under low temperature. We have found out the best parameter and analyzed the electrical characteristics of the oxide.
    In the second part, we investigate the performance improvement of the different gate oxide thickness and multi-channel poly-si TFT with rapid thermal annealing. The results of the experiment indicate that the thinner gate oxide thickness with RTA, the more improvement of electrical characteristics. This is because the high temperature of RTA can increase the quality of the oxide, reduce the defects of the oxide, and then improve the electrical characteristics.
    In addition, we research the electrical characteristics of multi-channel poly-si TFT. The electrical characteristics of the devices, such as threshold voltage and subthreshold swing, are improved with increasing the channel stripes. It also suppresses the short channel effect when the channel stripes increase.

    摘要(中文 摘要(英文) 誌謝 目錄 圖索引 表索引 第一章 序論 1.1 研究背景 1.2 研究動機 1.3 論文大綱 第二章 薄膜的生成與應用 2.1 簡介 2.2 CVD與PVD原理簡介 2.2.1 CVD(chemical vapor deposition)化學氣相沉積 2.2.2 PVD(physical vapor deposition)物理氣相沉積 2.3 電漿的物理原理 2.4 中空陰極管沉積原理 2.5 薄膜的製作 2.6 薄膜的分析 2.7 實驗結果與分析 2.7.1 各種氣體流量與沉積速率比較圖 2.7.2 TEOS/O2=65/100及TEOS/O2=65/200時在不同溫度下沉積速率及薄膜加熱前後蝕刻率的比較 2.7.3 依不同距離對沉積速率的比較圖 2.7.4 薄膜沉積的均勻性 2.7.5 不同Power與薄膜沉積速率的比較 2.7.6 傅立葉轉換紅外光光譜儀分析鍵結結構 第三章 快速熱退火對低溫多通道複晶矽薄膜電晶體處理的電性研究 3.1 簡 介 3.1.1半導體製程的退火(anneal) 3.1.2閘極氧化層厚度所產生的物理現象 3.1.3 Multiple Channel多通道結構 3.1.4短通道效應 3.2 薄膜電晶體製作 3.3 實驗結果與分析 3.3.1 不同閘極氧化層厚度之電性比較 3.3.2 快速熱退火對不同閘極氧化層厚度處理之電性比較 3.3.3 快速熱退火對多通道薄膜電晶體處理之電性比較 第四章 結論與未來工作 4.1 結論 4.2 未來工作 參考文獻

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