研究生: |
胡凱提 Kai-Ti Hu |
---|---|
論文名稱: |
實做於FPGA之適用於人臉偵測之高硬體效率色彩分割演算法 Field-Programmable Gate Array-Based Hardware-Efficient Color Segmentation Algorithm for Face Detection |
指導教授: |
阮聖彰
Shanq-Jang Ruan |
口試委員: |
許孟超
Mon-Chau Shie 陳維美 Wei-Mei Chen 吳晉賢 Chin-Hsien Wu 林昌鴻 Chang-Hong Lin |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2010 |
畢業學年度: | 98 |
語文別: | 英文 |
論文頁數: | 47 |
中文關鍵詞: | 色彩分割 、人臉偵測 、硬體實現 、元件可程式邏輯閘陣列(FPGA) |
外文關鍵詞: | color segmentation, face detection, hardware implementation, field-programmable gate array (FPGA) |
相關次數: | 點閱:237 下載:6 |
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在人臉偵測的數位影像系統中,膚色與唇色為人臉特徵中最明顯的資訊。但由於分析一張影像的整體色彩資訊相當的複雜且需要較大量的運算,因此許多人臉偵測技術並不適合直接實現於硬體中。
本篇論文研發出一個高效率且適合實現於硬體上的色彩分割演算法。在此演算法中,我們使用子色彩空間模型來取代整體色彩資訊,並且可以準確地偵測到膚色與唇色的色彩空間範圍。而在子色彩空間模型設計中,使用無浮點數運算的設計,如此一來不僅可以直接減少大量的運算,並且可節省設計的成本。此外,為了符合硬體設計程序此演算法也採用了模組化設計概念,以提升硬體架構之設計彈性。本篇論文所提出的演算法使用重要的膚色與唇色特徵分布,因此可以準確地促進人臉偵測之精準度。
為了驗證此演算法的硬體效率,我們將演算法實現於元件可程式邏輯閘陣列(FPGA)系統中,並且與現代先進的技術進行比較。實驗結果證實,我們所提出的演算法在元件可程式邏輯閘陣列(FPGA)系統中僅需使用3,202個邏輯閘,並且擁有較高的人臉偵測率。
Skin and lip color features of a human face are the most significant information for the face detection of the emerging applications in digital image systems. However, many face detection techniques may not be suitable for direct hardware implementation due to the high level of complexity for analyzing the overall color information in an image.
This paper develops a hardware-efficient color segmentation algorithm that is especially suitable to implement on hardware for face detection. We proposed the color sub-space model to detect the accurate skin/lip color ranges instead of the overall color information for efficient hardware design. Note that color sub-spaces are developed without floating-point operation to directly reduce the computational cost. Furthermore, the modulized design for the hardware design procedure is also adopted in the proposed algorithm. The significant skin/lip color features distribution can be accurately detected by using our proposed algorithm to facilitate the face detection.
The proposed algorithm was implemented on a field-programmable gate array (FPGA) system for verifying its efficiency. Compared with other state-of-the-art algorithms, the proposed algorithm can significantly decrease the computational cost of the hardware implementation by using color segmentation instead of the overall analysis of the color distribution. Experimental results have verified that our proposed FPGA system occupies only 3,202 logic cells, or about five times less than the current comparable FPGA system with better detection rate.
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