本論文提出應用於5G的極化碼(Polar Code)解碼器之超大型積體電路(VLSI)設計與實作，將快速簡化連續消除(Fast Simplified Successive Cancellation)作為演算法，在硬體設計上以提高吞吐量與降低硬體複雜度為研究目標，利用些許的解碼效能換取解碼時間的縮短，同時加入位元翻轉(Flip)與排序電路(Sorting)，縮減冗長的排序時間，降低解碼的錯誤率。
本論文使用Matlab作為演算法的軟體模擬平台，利用Xilinx Virtex-7 VC707之FPGA開發板作為硬體驗證平台，而晶片設計採用TSMC 40nm CMOS製程技術進行實作。
論文內容包含極化碼介紹、演算法模擬驗證、軟硬體效能比較及硬體架構介紹，最後記錄晶片實作的流程與結果。

This thesis proposes the design and implementation of a very large integrated circuit (VLSI) for a Polar Code decoder applied to 5G. Fast Simplified Successive Cancellation is used as an algorithm. In order to improve throughput and reduce hardware complexity as the research goals, use a little decoding performance in exchange for the shortening of decoding time, add bit-flip circuit and sorting circuit at the same time to reduce the lengthy sorting time and reduce the error rate.
In this thesis, Matlab is used as the software simulation platform of the algorithm, and the FPGA development board of Xilinx Virtex-7 VC707 is used as the hardware verification platform. The chip design is implemented by TSMC 40nm CMOS process technology.
The content of the thesis includes the introduction of polar codes, algorithm simulation verification, software and hardware performance comparison and hardware architecture introduction. Finally records the process and results of chip implementation.

[1] E. Arikan, "Channel polarization: A method for constructing capacity-achieving codes," 2008 IEEE International Symposium on Information Theory, 2008, pp. 1173-1177, doi: 10.1109/ISIT.2008.4595172.
[2] E. Arikan, "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels," in IEEE Transactions on Information Theory, vol. 55, no. 7, pp. 3051-3073, July 2009, doi: 10.1109/TIT.2009.2021379.
[3] R. Mori and T. Tanaka, "Performance of Polar Codes with the Construction using Density Evolution," in IEEE Communications Letters, vol. 13, no. 7, pp. 519-521, July 2009, doi: 10.1109/LCOMM.2009.090428.
[4] P. Trifonov, "Efficient Design and Decoding of Polar Codes," in IEEE Transactions on Communications, vol. 60, no. 11, pp. 3221-3227, November 2012, doi: 10.1109/TCOMM.2012.081512.110872.
[5] H. Zhang et al., "Parity-Check Polar Coding for 5G and Beyond," 2018 IEEE International Conference on Communications (ICC), 2018, pp. 1-7, doi: 10.1109/ICC.2018.8422462.
[6] G. He et al., "Beta-Expansion: A Theoretical Framework for Fast and Recursive Construction of Polar Codes," GLOBECOM 2017 - 2017 IEEE Global Communications Conference, 2017, pp. 1-6, doi: 10.1109/GLOCOM. 2017. 8254146.
[7] J. Guo, M. Qin, A. Guillén i Fàbregas and P. H. Siegel, "Enhanced belief propagation decoding of polar codes through concatenation," 2014 IEEE International Symposium on Information Theory, 2014, pp. 2987-2991, doi: 10.1109/ISIT.2014.6875382.
[8] G. Sarkis, P. Giard, A. Vardy, C. Thibeault and W. J. Gross, "Fast Polar Decoders: Algorithm and Implementation," in IEEE Journal on Selected Areas in Communications, vol. 32, no. 5, pp. 946-957, May 2014, doi: 10.1109/JSAC.2014.140514.
[9] M. Hanif and M. Ardakani, "Fast Successive-Cancellation Decoding of Polar Codes: Identification and Decoding of New Nodes," in IEEE Communications Letters, vol. 21, no. 11, pp. 2360-2363, Nov. 2017, doi: 10.1109/LCOMM.2017.2740305.
[10] P. Giard and A. Burg, "Fast-SSC-flip decoding of polar codes," 2018 IEEE Wireless Communications and Networking Conference Workshops (WCNCW), 2018, pp. 73-77, doi: 10.1109/WCNCW.2018.8369026.
[11] O. Afisiadis, A. Balatsoukas-Stimming and A. Burg, "A low-complexity improved successive cancellation decoder for polar codes," 2014 48th Asilomar Conference on Signals, Systems and Computers, 2014, pp. 2116-2120, doi: 10.1109/ACSSC.2014.7094848. 3GPP R1-1714179” Rate Matching Scheme for Polar Codes,” Samsung. Aug. 2017.
[12] X. Wang, T. Wang, J. Li and Y. Zhang, "Improved Multiple Bit-Flipping Fast-SSC Decoding of Polar Codes," in IEEE Access, vol. 8, pp. 27851-27860, 2020, doi: 10.1109/ACCESS.2020.2964904.
[13] C. Zhang, B. Yuan and K. K. Parhi, "Reduced-latency SC polar decoder architectures," 2012 IEEE International Conference on Communications (ICC), Ottawa, ON, 2012, pp. 3471-3475.
[14] J. Zeng, Y. Zhou, J. Lin and Z. Wang, "Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes," 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019, pp. 580-585, doi: 10.1109/ISVLSI.2019.00109.
[15] P. Giard et al., "PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 7, no. 4, pp. 616-629, Dec. 2017, doi: 10.1109/JETCAS.2017.2745704.
[16] C. Wong and H. Chang, "Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 7, pp. 566-570, July 2010, doi: 10.1109/TCSII.2010.2048481.