設計與實現一個基於VVC標準的畫面內預測硬體架構｜國立臺灣科技大學博碩士論文系統

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研究生：	楊仁甫 Jen-Fu Yang
論文名稱：	設計與實現一個基於VVC標準的畫面內預測硬體架構 Design and Implementation of a Hardware Architecture of Intra Prediction for the VVC Standard
指導教授：	林銘波 Ming-Bo Lin
口試委員:	陳郁堂 Yu-Tang Chen 林書彥 Shu-Yan Lin 蔡政鴻 Zheng-Hong Cai
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	中文
論文頁數：	95
中文關鍵詞：	影像壓縮、畫面內預測、FPAG 、ASIC
外文關鍵詞：	Video compression, Intra prediction, FPGA, ASIC
相關次數：	點閱：212 下載：0
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長久以來高解析度的影像傳輸和儲存問題一直是一個重大挑戰，為了解決此問題，聯合影像專家小組（Joint Video Experts Team, JVET）提出新一代的影像編碼技術H.266/VVC（Versatile Video Coding）。VVC較上一代H.265/HEVC（High Efficiency Video Coding）具有出色的壓縮效率，能有效解決影像資料傳輸和儲存的問題。VVC在畫面內預測方面做出了許多創新，如VVC引入了更多的預測模式，提高了預測的精確度。此外還加入了更精細的區塊劃分方式，以更好地適應畫面的變化，這些新特性都大大提升了影像壓縮的效率。
VVC的高壓縮率帶來的則是更複雜的編碼解碼演算法，如何在符合VVC標準的前提下，設計出高效能並且節省硬體面積的影像編碼解碼器，這對硬體設計及實現產生了巨大的挑戰。因此本論文主要設計與實現一個基於VVC標準的畫面內預測硬體架構，除了優化畫面內預測模組的設計之外，也提出驗證方法來確定電路的正確性，最後將結果與軟體做了詳細的比較和分析。
本研究架構已經在Xilinx Virtex 7系列的FPGA與ASIC上實現。在FPGA部分，依平行數量4、8及16之資源使用量與操作頻率分別為{29243 LUTs, 125MHz}、{58531 LUTs, 125MHz}及{116344LUTs, 100MHz}。ASIC設計使用了TSMC 0.18 m的標準元件庫，合成後資源大小依平行數量4、8及16，其面積與操作頻率分別為{3566786 m2, 125MHz}、{6765176 m2, 125MHz}及{13238669 m2, 125MHz}，佈局後晶片總面積為2858.22 m × 2858.16 m，等效362606個邏輯閘，操作頻率為113Mhz。本研究成果證明了此設計在提高影像壓縮效率的同時，也具有實用的硬體實現可行性。

The problem of transmission and storage of high-resolution video has been a major challenge for a long time. To address this issue, Joint Video Experts Team proposed a new generation of video coding technology called H.266/VVC (Versatile Video Coding). VVC offers remarkable compression efficiency compared to previous standard, H.265/HEVC (High Efficiency Video Coding), making it more effective in tackling the problems associated with video data transmission and storage. VVC has made many innovations in intra prediction. For instance, VVC introduces more predictive modes to enhance the accuracy of prediction. In addition, a finer block division method has been added to better adapt to scene variations. These new features greatly enhance video compression efficiency.
The high compression ratio of VVC comes with more complex encoding and decoding algorithms. Designing a video codec that meets the VVC standard while achieving high performance and saving hardware resources presents a significant challenge for hardware design and implementation. Therefore, this thesis primarily focuses on designing and implementing hardware architecture of intra prediction based for the VVC standard. In addition to optimizing the design of the intra prediction module, a method of verification is proposed to confirm the correctness of the circuit. Finally, the results were compared and analyzed in detail with the software.
This study has been implemented on Xilinx Virtex 7 series FPGA and ASIC. In the FPGA, according to the number of parallels 4, 8, and 16, resource usage and operating frequency are {29243 LUTs, 125MHz}, {58531 LUTs, 125MHz} and {116344 LUTs, 100MHz} respectively. The ASIC design uses TSMC 0.18 m standard cell library. According to the parallel numbers 4,8, and 16, area and operating frequency are {3566786 m2, 125MHz}, {6765176 m2, 125MHz} and {13238669 m2, 125MHz} respectively. After layout, the total chip area is 2858.22 m × 2858.16 m, which is equivalent to 362606 logic gates, and the operating frequency is 113Mhz. The results of this paper demonstrate that this design not only improves the efficiency of video compression but also has the feasibility of practical hardware implementation meanwhile.

致謝    IV
摘要    V
ABSTRACT    VI
目錄    VIII
圖目錄    XII
表目錄    XV
第1章    緒論    1
1    研究動機    1
2    研究方向    1
3    章節安排    2
第2章    影像壓縮概念與VVC標準介紹    3
1    影像壓縮概述    3
1.1    影像壓縮編碼架構    3
1.2    影像壓縮解碼架構    4
2    影像壓縮冗餘及處理技術介紹    5
2.1    感知冗餘    5
2.2    空間冗餘    7
2.3    時間冗餘    10
2.4    統計冗餘    11
3    影像解碼時間分析    13
4    VVC標準介紹    13
5    VVC與HEVC標準比較    15
5.1    CTU區塊大小    15
5.2    區塊分割技術    16
5.3    畫面內預測    16
第3章    畫面內預測演算法介紹    22
1    基本參數定義    22
2    直流預測模式    23
2.1    計算方式    23
3    平面預測模式    24
3.1    水平預測計算方式    25
3.2    垂直預測計算方式    25
3.3    平面預測模式計算結果    26
4    角度預測模式    26
4.1    參數計算    28
4.2    準備參考像素    30
4.3    準備濾波係數    33
4.4    計算結果    34
5    位置依賴的畫面內預測組合    36
5.1    直流和平面模式計算    36
5.2    水平與垂直模式計算    37
5.3    角度模式計算    38
第4章    畫面內預測硬體設計與實現    40
1    畫面內預測接腳定義    40
2    參數化設計    41
3    畫面內預測模組    42
4    參數準備模組    43
4.1    基本參數準備模組    44
4.2    直流預測模式參數準備模組    45
4.3    平面預測模式參數準備模組    46
4.4    角度預測模式參數準備模組    47
4.5    位置依賴的畫面內預測組合參數準備模組    47
5    記憶體位址產生模組    48
6    直流預測模組    51
7    平面與角度預測模組    52
8    位置依賴的畫面內預測組合模組    54
第5章    驗證方法    56
1    基本介紹    56
1.1    VTM介紹    56
1.2    Xiph.org基金會    56
1.3    Elecard StreamEye Studio介紹    56
2    驗證步驟    57
2.1    驗證影片選擇    57
2.2    影片編碼    58
2.3    提取畫面內預測資料    58
2.4    驗證結果    60
第6章    FPGA與ASIC模擬與實現結果    61
1    FPGA設計與實現結果    61
1.1    功能模擬驗證結果    61
1.2    FPGA合成結果    63
1.3    邏輯閘階級模擬驗證結果    64
1.4    佈局後模擬結果    64
1.5    FPGA佈局後結果    65
2    ASIC設計與實現結果    66
2.1    功能模擬驗證結果    67
2.2    Design Compiler合成結果    67
2.3    邏輯閘階級模擬驗證結果    67
2.4    佈局後模擬結果    68
2.5    晶片佈局結果    69
2.6    DRC與LVS結果    71
3    晶片效能分析    71
3.1    硬體直流預測模式分析    72
3.2    硬體平面與角度預測模式分析    72
3.3    軟體效能分析    72
4    效能比較結果    74
4.1    FPGA和ASIC效能結果    74
4.2    軟體比較結果    75
4.3    FPGA相關論文比較結果    76
4.4    ASIC相關論文比較結果    77
第7章    結論與未來展望    78
參考文獻    79

                                

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