簡易檢索 / 詳目顯示

回結果列表
研究生： 方孟彥
Meng-Yan Fang
論文名稱： 低功耗寬鎖頻範圍注入鎖定除二除頻器及小型電容耦合注入鎖定除二除頻器
Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider and Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider
指導教授： 張勝良
Sheng-Lyang Jang
莊敏宏
Miin-Horng Juang
口試委員: 徐敬文
Ching-Wen Hsue
王煥宗
Huan-Chun Wang
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 114
中文關鍵詞： 注入鎖定除頻器
外文關鍵詞： injection-locked frequency divider
相關次數： 點閱：229  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  •  上一筆

    • 本論文提出三個除頻器，第一個電路先描述一個低功耗除二寬鎖頻範圍注入鎖定除頻器，使用 TSMC 0.18 μm CMOS製程。此注入鎖定除頻器是除二電路。量測結果為供應電壓0.4 V，核心電流為3.8 mA，核心功耗為1.52 mW。當注入訊號為0 dBm時，其除二鎖頻範圍為7.2至10.8 GHz。
    第二個電路描述一個除三注入鎖定除頻器，此電路是使用TSMC 0.18 μm SiGe BiCMOS製程，此注入鎖定除頻器是除三電路，量測結果為供應電壓0.9 V，當注入訊號為0 dBm時，其總鎖頻範圍為6.4 GHz至12.6 GHz，總功耗為6.32 mW。
    最後一個電路是描述一個使用3D電感小型除二寬鎖頻範圍注入鎖定除頻器，是使用TSMC 0.18 μm CMOS製程，量測結果為供應電壓1 V，而可調範圍1.86至2.27 GHz，核心電流為10.22 mA，核心功耗為10.22 mW。當注入訊號為0 dBm時，其鎖頻範圍為1.5 to 7.4 GHz。

    Firstly, this thesis presents a new divide-by-2 ILFD, which is implemented in the TSMC 0.18 μm 1P6M CMOS process. The divide-by-2 capacitive cross-coupled ILFD has wide locking range at low power consumption by lowering the gate bias of the capacitive cross-coupled transistor. At the drain-source bias of 0.4V and at the incident power of 0 dBm, the locking range is 3.6 GHz (36.28%) from 7.2 to 10.8GHz at the power consumption of 1.52mW. The die area is 1.2 ×0.951 mm2.
    The second circuit is a wide locking range divide-by-3 LC injection-locked frequency divider (ILFD) in the TSMC 0.18 μm SiGe BiCMOS process. The divide-by-3 ILFD uses a cross-coupled NMOS pair, an injection MOSFET pair and a 6th order RLC resonator. The divide-by-3 ILFD has two oscillation frequency bands. The ILFD-core power consumption is 6.318 mW. At the drain-source bias of 0.9 V, and at the incident power of 0 dBm, a wide locking range 6.2GHz (65.26％) from 6.4 to 12.6 GHz is obtained by over-lapping the locking ranges at a fixed bias condition. The die area is 1.1×0.84 mm2.
    Finally, a lower power and wide locking range divide-by-2 capacitive cross-coupled injection-locked frequency divider (ILFD) is implemented in the TSMC standard 0.18 μm CMOS process. The ILFD is based on a capacitive cross-coupled VCO with one injection MOSFET for coupling the external signal to the resonator. The ILFD uses one 3-dimensional inductor to reduce the die area. At the supply voltage of 1V, the divider’s free-running frequency is 2.27 GHz, and at the incident power of 0 dBm the locking range is about 5.9GHz (132.58％) from 1.5GHz to 7.4 GHz. The core power consumption is 10.22mW. At low power mode, the ILFD has higher figure of merit. The die area is 0.719×0.637 mm2.

    中文摘要 II Abstract III 誌謝 V List of Contents VI List of Figures VIII List of Tables XI Chapter 1 Introduction 1 1.1 BACKGROUND 1 1.2 THESIS ORGANIZATION 4 Chapter 2 Principles and Design concepts of Voltage Controlled Oscillators 6 2.1 INTRODUCTION 6 2.2 THE OSCILLATOR THEORY 10 2.3 CATEGORIZATION OF OSCILLATORS 13 2.3.1 RESONATORLESS OSCILLATORS 14 I. RING OSCILLATOR 14 II. RELAXATION OSCILLATOR 16 2.3.2 LC-TANK OSCILLATORS 17 I. COLPITTS AND HARTLEY OSCILLATORS 17 II. NEGATIVE -GM OSCILLATORS 18 2.4 VARACTORS 20 2.4.1 MOS VARACTORS 20 I. INVERSION-MODE PMOS VARACTOR (I-MOS) 22 II. ACCUMULATION-MODE PMOS VARACTOR (A-MOS) 22 2.5 INDUCTOR AND TRANSFORMERS 23 2.5.1 SPIRAL INDUCTOR 23 2.5.2 THE TRANSFORMER 29 2.6 PHASE NOISE AND Q FACTOR IN OSCILLATORS 34 2.6.1 LINEAR TIME INVARIANT (LTI) MODEL - (THE LESSON’S MODEL) 37 2.6.2 KINDS OF NOISE 40 2.6.3 PHASE NOISE IN WIRELESS COMMUNICATIONS 44 2.6.4 QUALITY FACTOR 47 Chapter 3 Design of Injection Locked Frequency Frequency Divider 50 3.1 INJECTION LOCKING FREQUENCY DIVIDER 50 3.1.1 PRINCIPLE OF INJECTION LOCKED FREQUENCY DIVIDER 51 3.1.2 LOCKING RANGE 53 3.1.3 SWITCH ILFD 56 Chapter 4 Low Power Wide-Locking Range Divide-by-2 Injection-Locked Frequency Divider 58 4.1 INTRODUCTION 58 4.2 CIRCUIT DESIGN 60 4.3 MEASUREMENT RESULTS 61 Chapter 5 Triple-Resonance Divide-by-3 Injecion-Locked Frequency Divider Using Single Varactor Bias 67 5.1 INTRODUCTION 67 5.2 CIRCUIT DESIGN OF THE PROPOSED ILFD 68 5.3 MEASUREMENT AND DISCUSSION 70 Chapter 6 Small Die Area Capacitive Cross-coupled Injection-Locked Frequency Divider 84 6.1 INTRODUCTION 84 6.2 CIRCUIT DESIGN 85 6.3 MEASUREMENT RESULTS 87 Chapter 7 Conclusion 94 References 96

    [1] J. Roggers, C. Plett, Radio Frequency Integrated Circuit Design, Artech House, 2003.
    [2] N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
    [3] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
    [4] D. Hauspie, E.-C. Park, and J. Craninckx, “Wide-band VCO with simultaneous switching of frequency band, active core, and varactor size,” IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1472–1480, Jul. 2007.
    [5] J. Tang and D. Kasperkovitz, Oscillator Design Efficiency: A New Figure Of Merit For Oscillator Benchmarking.
    [6] N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
    [7] B.Razavi, RF Microelectronics, Prentice Hall PTR 1998.
    [8] A. Porret, T. Melly, C. Enz, and E, Vittoz, “Design of high-Q varactors for low-power wireless applications using a standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, pp. 337-345, Mar. 2000.
    [9] F. Svelto, P. Erratico, S. Manzini, and R. Castello, “A metal oxide semiconductor varactor,” IEEE Electron Device Lett., vol. 20, pp. 164-166, Apr. 1999.
    [10] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, pp. 905-910, Jun. 2000.
    [11] T. Soorapanth, C. Yue, D. Shaeffer, T. Lee, and S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” in 1998 Symp. VLSI Circuits Dig. Tech. Papers, pp. 22-23. Jun. 1998.
    [12] J. Aguilera, and R. Berenguer, “Design and test of integrated inductors for RF applications,” Kluwer Academic Publishers, 2004.
    [13] J. Craninckx, and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, 1998.
    [14] Y. K. Koutsoyannopoulos and Y. Papananos, “Systematic analysis and modeling of integrated inductors and transformers in RF IC design,” IEEE Trans. Circuits and System-II, vol. 47, no. 8, pp. 699-713, 2000.
    [15] A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
    [16] Y. Koutsoyannopoulos, “Novel Si integrated inductor and transformer structure for RF IC design,” Proc. ISCAS , vol. 2, pp. 573-576, June. 1999.
    [17] C. Tang, C. Wu, and S. Liu, “Miniature 3-D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-480, 2002
    [18] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Trans. on Parts, Hybrids and Packaging, vol. PHP-10, no.2, pp. 101-109, 1974.
    [19] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
    [20] John Starr Hamel, “LC tank Voltage Controlled Oscillator Tutorial,” Waterloo, Ontario, Canade, 2005
    [21] D. B. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, no. 2, pp. 329–330, Feb. 1966.
    [22] A. Hajimiri and T. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
    [23] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
    [24] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
    [25] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
    [26] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
    [27] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
    [28] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
    [29] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
    [30] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
    [31] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
    [32] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
    [33] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
    [34] H. Wu, “Signal generation and processing in high-frequency/high-speed silicon- based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
    [35] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
    [36] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits,vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
    [37] K. Yamamoto and M. Fujishima, “55GHz CMOS frequency dividerwith 3.2GHz locking range” ESSCC, pp. 135-138, Aug. 2004.
    [38] H. Wu and A. Hajimiri, “A 19 GHz 0.5mW 0.35 μm CMOS frequencydivider with shunt-peaking locking-range enhancement,” in IEEE Int.Solid-State Circuits Conf., pp. 412-413, Feb. 2001.
    [39] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee, and M.-H. Juang, “A wide locking range and low voltage CMOS direct injection-locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 5, pp. 299-301, May 2006.
    [40] S.-L. Jang, Z.-H. Wu, C.-W. Hsue and H.-F. Teng,” Wide-locking range dual-band injection-locked frequency divider,” Microw. Opt. Technol. Lett., vol. 55, 10, pp. 2333–2337, Oct. 2013.
    [41] S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang," Injection-locked frequency divider using injection mixer DC-biased in sub-threshold," IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, Mar. 2015.
    [42] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, Jun. 1999.
    [43] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-μm CMOS technology,” in Symp., VLSI Circuits Dig. Tech. Papers, pp. 259–262, Jun. 2003.
    [44] S.-L. Jang, S.-S. Huang, J.-F. Lee and M.-H. Juang,” LC-tank Colpitts injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., pp.560-562, Aug. 2008.
    [45] S. Lee, S. Jang, and C. Nguyen, “Low-power-consumption wide-locking-range dual-injection-locked 1/2 divider through simultaneous optimization of VCO loaded Q and current,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 10, pp. 3161–3168, Oct. 2012.
    [46] N. Mahalingam, K. Ma, K. S. Yeo, and W. M. Lim, “Coupled dual LC tanks based ILFD with low injection power and compact size,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 2, pp. 105-107, Feb. 2014.
    [47] S.-L. Jang, F.-B. Lin,and J.-F. Huang,” Wide-band divide-by-2 injection-locked frequency divider using MOSFET mixers DC-biased in subthreshold region,” Int. J. Circ Theor App, 12, Jan. 2015.
    [48] S.-L. Jang, C.-C. Liu, and J.-F. Huang,” Divide-by-3 injection-locked frequency divider using two linear mixers,” IEICE Trans. Electron., Vol.E93-C, No.1, pp. 136-139, Jan. 2010.
    [49] S.-L. Jang, and C.-W. Chang,” A 90nm CMOS LC-tank divide-by-3 injection-locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.229-231, April, 2010.
    [50] S.-L. Jang, Y.-S. Chen, C.-W. Chang, and C.-C. Liu,” A wide-locking range ÷3 injection-locked frequency divider using linear mixer,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.390-392, Jul. 2010.
    [51] Y.-T. Chen., M.-W. Li, H.-C. Kuo, T.-H. Huang, and Chuang H.-R. , “Low-voltage K-band divide-by-3 injection-locked frequency divider with floating-source differential injector,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 160–167, 2012.
    [52] S.-L. Jang and J.-H Hsieh, ” A wide-locking range ÷3 injection-locked frequency divider using concurrent injection mechanisms,” Analog Integr Circ Sig Process., Vol. 77, pp 593-598, 2013.
    [53] Wu J.-W, C.-C. Chen, H.-W. Kao, J.-K. Chen, and M.-C. Tu,”Divide-by-three injection-locked frequency divider combined with divide-by-two locking,” IEEE Microw. Wireless Compon. Lett., pp. 590-592, Nov. 2013.
    [54] K.-H. Chien, J. Y. Chen and H. K. Chiou, “Designs of K-band divide-by-2 and divide-by-3 injection-locked frequency divider with Darlington topology,” IEEE Trans. Microw. Theory Tech., vol. 99, 2015.
    [55] S.-L. Jang and C.-Y. Chuang, ”Wide-locking range ÷3 series-tuned injection-locked frequency divider,” Analog Integr Circ Sig Process, Vol. 76, 1, pp. 111-116, Jan. 2013.
    [56] S.-L. Jang ” Divide-by-3 injection-locked frequency dividers using dual-resonance resonator,” Analog Integr Circ Sig Process., Vol. 85, Issue 2, pp. 335-341, Nov. 2015.
    [57] S.-L. Jang, W.-C. Cheng and C.-W. Hsue, "Wide-locking range divide-by-3 injection-locked frequency divider using 6th-order RLC resonator," published online, IEEE Transactions on Very Large Scale Integration Systems 2016.
    [58] H. Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3 injection-locked frequency divider,” in IEEE ISSCC Dig. Tech. Papers, pp.27-29, Feb. 2006.
    [59] S.-L. Jang, C.-Y. Lin, and M.-H. Juang,”Enhanced locking range technique for a divide-by-3 differential injection-locked Frequency divider,” Electron. Lett., vol. 51, 19, pp. 456-458, 2015.
    [60] S.-L. Jang, and C.-Y. Lin,”A wide-locking range Class-C injection-locked frequency divider,” Electron. Lett., vol. 50, 23, pp.1710-1712, 2014.
    [61] M. Tiebout,“A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits,vol. 39, no. 7, pp. 1170-1174, Jul. 2004.
    [62] S.-L. Jang, C.-W. Chang, C.-F. Lee, and J.-F. Huang,” Divide-by-3 LC injection locked frequency divider implemented with 3D inductors,” IEICE Trans. on Electronics. Vol.E91-C, No.6, pp.956-962, Jun. 2008.
    [63] S.-L. Jang, M.-Hs. Suchen, and C.-F. Lee,” Colpitts injection locked frequency divider implemented with a 3D helical transformer” IEEE Microw. Wireless Compon. Lett. vol. 18, no. 6, pp.410-412, June, 2008.
    [64] S.-L. Jang, C.-C. Liu and C.-W. Tai,” Implementation of 6-port 3D transformer in injection-locked frequency divider,” IEEE Int. VLSI- DAT, 2009.
    [65] S.-L. Jang, Y.-J. Chen, C.-H. Fang and W. C. Lai, ” Enhanced locking range technique for frequency divider using dual-resonance RLC resonator,” Electronics Letters ,vol. 51, no. 23, 05, pp. 1888-1889, Nov. 2015.
    [66] S.-L. Jang, X.-Y. Hang, and W.–T. Liu,” Review: capacitive cross-coupled injection-locked frequency dividers,” Analog Integr Circ Sig Process. Vol. 88, no.1, pp 97-104, 2016.
    [67] S.-L. Jang, X.-Y. Hang, and W.–T. Liu, ” Review: capacitive cross-coupled injection-locked frequency dividers,” Analog Integr Circ Sig Process. Vol. 88, no.1, pp 97-104, 2016.
    [68]S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang," Injection-locked frequency divider using injection mixer DC-biased in sub-threshold," IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, March 2015.
    [69]H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813–821, June 1999.

    無法下載圖示 全文公開日期 2021/08/11 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館：臺灣博碩士論文系統)
    QR CODE