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研究生: 卓躍
Yueh Cho
論文名稱: 抵禦基於布林滿足性攻擊之臨界值邏輯鎖定技術
SAT Attack Resistant Logic Locking for Threshold Logic
指導教授: 陳勇志
Yung-Chih Chen
口試委員: 方劭云
Shao-Yun Fang
劉一宇
Yi-Yu Liu
林政宏
Cheng-Hung Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 英文
論文頁數: 50
中文關鍵詞: 臨界值邏輯邏輯鎖定整數線性規劃布林滿足性攻擊
外文關鍵詞: threshold logic, logic locking, integer linear programming, SAT attack
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邏輯鎖定是一種用於矽智財、積體電路的保護技術,防止硬體安全問題。近年,受惠於硬體製造技術的進步以及在機器學習中的應用,臨界值邏輯再次引起了學術界的關注。儘管有許多用於臨界值邏輯的電子設計自動化技術,但目前尚無針對臨界值邏輯的邏輯鎖定研究。在這篇論文中,我們首先提出了兩種用於鎖定臨界值邏輯閘以抵抗布林滿足性攻擊的方法,布林滿足性攻擊是對邏輯鎖定最具威脅的攻擊技術之一。第一種方法是基於整數線性規劃的方法,將臨界值邏輯閘加密問題轉換為整數線性規劃問題。由於整數線性規劃不適用於大型臨界值邏輯閘,因此我們進一步提出啟發式方法提高其效率。第二種方法是一種非基於整數線性規劃的方法,可以針對特定的臨界值邏輯閘進行鎖定或混淆,以抵抗布林滿足性攻擊和移除攻擊。基於臨界值邏輯閘鎖定方法,我們進一步提出了用於臨界值邏輯閘網路的鎖定流程。實驗結果顯示,基於整數線性規劃的方法,在可接受的執行時間內成功地加密具有少於八個輸入的臨界值邏輯閘。此外,臨界值邏輯閘網路的鎖定流程有效地使已鎖定的臨界值邏輯閘網路能夠抵抗布林滿足性攻擊。


Logic locking is an IP/IC protection technique that can prevent hardware security issues. Recently, threshold logic has re-attracted attention from researchers due to its promising hardware implementation and its applications in machine learning. While several electronic design automation techniques for threshold logic, research on logic locking specifically for threshold logic is still lacking. Therefore, in this thesis, we first propose two methods for locking a threshold logic gate (TLG) to resist SAT attack, which is one of the most powerful attack techniques against logic locking. The first method is an integer linear programming (ILP)-based method that formulates the problem of TLG encryption as an ILP problem. Since the ILP formulation is not scalable to large TLGs, we further improve its efficiency with some heuristics. The second method is a non-ILPbased method that encrypts and obfuscates specific TLGs to defend against SAT attack and Removal attack simultaneously. Based on the TLG locking methods, we further present an encryption flow for threshold logic networks (TLNs). The experimental results show that the ILP-based method can successfully encrypt the TLGs having less than 8 inputs with acceptable execution time. Additionally, the proposed TLN encryption method is effective in making the locked TLNs achieve good resistance against SAT attack.

Abstract in Chinese . . . . . . . . . . . . . . . iii Abstract in English . . . . . . . . . . . . . . . iv Acknowledgements . . . . . . . . . . . . . . . . v List of Figures . . . . . . . . . . . . . . . . . viii List of Tables . . . . . . . . . . . . . . . . . ix Chapter 1. Introduction . . . . . . . . . . . . . 1 Chapter 2. Preliminaries . . . . . . . . . . . . 6 2.1 ILP-based TLG and 2-TLG identification. . . . 6 2.2 Logic locking . . . . . . . . . . . . . . . 9 2.3 SAT attack . . . . . . . . . . . . . . . . . 10 2.4 SAT attack resilient logic locking . . . . . 12 Chapter 3. Proposed Methods . . . . . . . . . . . 15 3.1 Logic locking for TLGs . . . . . . . . . . . 15 3.1.1 Straightforward logic locking for a TLG . . 15 3.1.2 ILP-based method for TLG locking . . . . . 17 3.1.3 Non-ILP-based method for AND/OR TLG locking 21 3.2 Logic locking for TLNs . . . . . . . . . . . 25 3.2.1 TLG obfuscation . . . . . . . . . . . . . . 25 3.2.2 TLN encryption flow . . . . . . . . . . . . 27 Chapter 4. Experimental Results . . . . . . . . . 31 Chapter 5. Conclusion . . . . . . . . . . . . . . 38 References . . . . . . . . . . . . . . . . . . . 39

[1] R. O. Winder, “Single stage threshold logic,” in Proc. the Second Annual Symp. on Switching Circuit Theory and Logical Design, pp. 321–332, 1961.
[2] S.-Y. Lee, N.-Z. Lee, and J.-H. R. Jiang, “Searching parallel separating hyperplanes for effective compression of threshold logic networks,” in 2019 IEEE/ACM International Conference on ComputerAided Design (ICCAD), pp. 1–8, 2019.
[3] S. N. Mozaffari et al., “A generalized approach to implement efficient cmos-based threshold logic functions,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, pp. 946–959, March 2018.
[4] J. A. Roy, F. Koushanfar, and I. L. Markov, “EPIC: Ending piracy of integrated circuits,” in Proc. Design, Automation and Test in Europe Conf., pp. 1069–1074, 2008.
[5] P. Subramanyan, S. Ray, and S. Malik, “Evaluating the security of logic encryption algorithms,” in 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 137–143, IEEE, 2015.
[6] C.-H. Liu et al., “Threshold function identification by redundancy removal and comprehensive weight assignments,” IEEE Trans. on Computer-Aided Design, Early Access, 2018.
[7] A. Neutzling et al., “Effective logic synthesis for threshold logic circuit design,” IEEE Trans. Computer-Aided Design, vol. 38, pp. 926–937, May 2019.
[8] L.-C. Zheng, H.-J. Chang, Y.-C. Chen, and J.-Y. Jou, “1st-order to 2nd-order threshold logic gate transformation with an enhanced ilp-based identification method,” in Proc. Asia South Pacific Design Automation Conf., pp. 469–474, 2021.
[9] T.-Y. Yeh, Y. Cho, and Y.-C. Chen, “An effective and efficient heuristic for rational-weight threshold logic gate identification,” in 2023 Design, Automation Test in Europe Conference Exhibition (DATE), pp. 1–6, 2023.
[10] M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Security analysis of anti-sat,” in 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 342–347, 2017.
[11] M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Removal attacks on logic locking and camouflaging techniques,” IEEE Transactions on Emerging Topics in Computing, vol. 8, no. 2, pp. 517– 532, 2020. 39
[12] S. Muroga, Threshold logic and its applications. New York, NY: John Wiley, 1971.
[13] J. Rajendran, H. Zhang, C. Zhang, G. S. Rose, Y. Pino, O. Sinanoglu, and R. Karri, “Fault analysisbased logic encryption,” IEEE Transactions on Computers, vol. 64, no. 2, pp. 410–424, 2015.
[14] J. Rajendran, Y. Pino, O. Sinanoglu, and R. Karri, “Security analysis of logic obfuscation,” in DAC Design Automation Conference 2012, pp. 83–89, 2012.
[15] Y.-C. Chen, “Smartlock: SAT attack and removal attack-resistant tree-based logic locking,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E103.A, pp. 733–740, 05 2020.
[16] M. Yasin, B. Mazumdar, O. Sinanoglu, and J. Rajendran, “Camoperturb: Secure ic camouflaging for minterm protection,” in 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8, 2016.
[17] Y. Xie and A. Srivastava, “Anti-SAT: Mitigating SAT attack on logic locking,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 38, no. 2, pp. 199–207, 2019.
[18] M. Yasin, B. Mazumdar, J. J. V. Rajendran, and O. Sinanoglu, “SARLock: SAT attack resistant logic locking,” in 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 236–241, 2016.
[19] Gurobi Optimization, LLC, “Gurobi Optimizer Reference Manual,” 2022.
[20] “IWLS 2005 benchmark suite,” 2005.
[21] S. Yang, “Logic synthesis and optimization benchmarks, version 3.0,” Tech. Report, 1991.
[22] Berkeley logic synthesis and verification group, “ABC: A system for sequential synthesis and verification, release 70930,” 2007.

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全文公開日期 2029/08/15 (校外網路)
全文公開日期 2029/08/15 (國家圖書館:臺灣博碩士論文系統)
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