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研究生: 詹子增
Zi-zeng Zhan
論文名稱: 雙模式降壓型功率因數修正器之研製
Study and Implementation of a Dual-Mode Buck Power Factor Corrector
指導教授: 羅有綱
Yu-kang Lo
邱煌仁
Huang-Jen Chiu
口試委員: 林景源
Jing-yuan Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 中文
論文頁數: 92
中文關鍵詞: 雙模式功率因數修正器邊界導通模式
外文關鍵詞: Dual-mode, power factor corrector, boundary conduction mode
相關次數: 點閱:231下載:10
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  • 本論文主要目的係將雙模式控制法運用在降壓型主動功率因數修正器,當輕載時電路會操作在邊界導通模式,降低輕載操作的切換損失。當重載時操作於連續導通模式,電感電流峰值電流較低,電路功率元件之導通損耗較小。
    本論文先就兩導通模式之功率因數修正器做分析,量測出各個負載下之效率分佈,因此可找出雙模式降壓型功率因數修正器的轉態點。最後實際製作一 150 W 雙模式降壓型功率因數修正器,以實驗驗證論文中所提之分析與設計考量是否合理。實作電路之控制 IC 使用意法半導體所生產的 L6561,搭配自製外加控制電路,功率級採用降壓型轉換器電路架構。經測量結果證明,輕載及半載下確實操作於邊界導通模式而減少切換損耗;而重載下操作於連續導通模式而減少導通損耗。


    This thesis aims to study a dual-mode buck active power factor corrector (PFC). Under light-load condition, the circuit is operated at boundary conduction mode (BCM) to reduce the switching loss. Otherwise, the circuit is operated at continuous conduction mode (CCM) under heavy-load condition. The peak inductor current is reduced and the conduction loss is less.
    First, the loss distributions of the PFC at various load levels for both BCM and CCM are analyzed. Therefore, a transition point can be found to switch between the two control modes. A 150-W dual-mode buck PFC prototype is built to verify the circuit analysis and design considerations. The control circuits of the laboratory prototype are implemented by using the STMicroelectronics chip L6561 and additional external circuits. Experimental results show that the studied PFC actually operates under BCM from light-load to half-load conditions to reduce the switching loss, and under CCM at heavy loads to reduce the conduction loss.

    摘要 i Abstract ii 誌謝 iii 目錄 v 符號索引 vii 圖目錄 xi 表目錄 xvi 第一章  緒論 1 1.1 研究背景 1 1.2 論文大綱 4 第二章  功率因數修正原理 5 2.1 功率因數與總諧波失真之定義 5 2.2 功率因數修正器之種類 8 2.2.1 被動式功率因數修正器 8 2.2.2 主動式功率因數修正器 10 2.3 降壓型功率因數修正器架構 11 2.4 功率因數修正器之控制模式 14 第三章  雙模式降壓型功率因數修正器原理分析 20 3.1 降壓型功率因數修正轉換器之電流失真 20 3.2 降壓型功率因數修正器工作原理 21 3.2.1 邊界導通模式降壓型功率因數修正器工作原理 22 3.2.2 連續導通模式降壓型功率因數修正器工作原理 26 3.3 雙模式降壓型功率因數修正器 32 3.3.1 控制IC L6561 32 3.3.2 固定截止時間控制機制 34 3.3.3 雙模式降壓型功因修正器控制電路機制 37 第四章  電路設計實例 44 4.1 雙模式降壓型功率因數修正器電路之規格 44 4.2 功率級元件設計 44 4.3 外加自製控制電路參數設計 53 第五章  實驗結果與分析 60 5.1 實驗波形 60 5.2 實驗數據 68 5.3 電路損耗分析 73 5.3.1 功率開關Q之損耗 74 5.3.2 輸出二極體D之損耗 78 5.3.3 電流偵測電阻Rsense之損耗 79 5.3.4 輸入橋式整流器之損耗 80 5.3.5 輸出電感L之損耗 81 5.3.6 EMI濾波器之損耗 85 5.3.7 功率損耗分佈 85 第六章  結論與未來展望 88 6.1 結論 88 6.2 未來展望 89 參考文獻 90

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