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| 研究生： |
廖育紳 Yu-Shen Liao |
|---|---|
| 論文名稱： |
倍頻器及注入鎖定高階除頻器 Frequency Doubler and High-Modulus Injection-Locked Frequency Dividers |
| 指導教授： |
張勝良
Sheng–Lyang Jang |
| 口試委員: |
莊敏宏
Miin-Horng Juang 溫俊瑜 Jiun-Yu Wen 宋峻宇 Jiun-Yu Sung |
| 學位類別： |
碩士 Master |
| 系所名稱： |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
| 論文出版年： | 2021 |
| 畢業學年度： | 109 |
| 語文別： | 英文 |
| 論文頁數： | 110 |
| 中文關鍵詞： | 除頻器 |
| 外文關鍵詞： | divider |
| 相關次數： | 點閱：210 下載：10 |
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在RF射頻收發機中，頻率合成器的特性是很重要的角色，其中內部包含了相位偵測器(PFD)、充電幫浦(CP)、迴路濾波器(LF)、壓控振盪器(VCO)、除頻器(FD)，而其中又以壓控振盪器和注入鎖定除頻器的特性為主要的電路。壓控振盪器需要低相位雜訊來避免相鄰雜訊訊號經由混波轉換的干擾，壓控振盪器的輸出在經由除頻器來達到降頻的工作，所以除頻器必須有高的操作頻率與頻寬。本篇論文呈現各種高性能注入鎖定除頻器(ILFD)的設計。
首先，本篇量測倍頻器使用了台積電0.18 μm BiCMOS SiGe 製程。此倍頻器為具有負柵極偏壓的金氧半場效電晶體倍頻器，由D類壓控電壓震盪器生成的內部信號作為輸入電壓，再藉由異質接面雙載子電晶體作為二極管的整流器產生負柵極偏壓來倍頻。壓控電壓震盪器提供的電壓振幅是供應電壓的三倍，並且具有高負向電壓在，此電路產生4.34 GHz到4.17GHz之訊號，並由在尾端注入訊號，可將D類壓控電壓震盪器當成除二注入鎖定除頻器，讓倍頻器提供相位雜訊和追蹤注入訊號的訊號，此電路的面積為1.19×1.15 mm2。
其次，本篇量測一個使用台積電0.18 μm製程之互補式金氧半導體除十六注入鎖定除頻器，此除頻器是由電流型邏輯電路除四除頻器疊接電容交叉耦合式之除四注入鎖定除頻器構成，除十六注入鎖定除頻器在注入訊號強度為0 dBm的情況下有10.81 GHz到12.82 GHz的除頻範圍，其功率消耗為 12.5mW。除十六注入鎖定除頻器使用有寬注入鎖定範圍的電流型邏輯電路除四除頻器來跟隨LC注入鎖定除頻器輸出的頻率，此電路的面積為1.2×1.198 mm2。此注入鎖定除頻器還可以當成除二十四注入鎖定除頻器和除八注入鎖定除頻器。
第三，本篇量測一個使用台積電0.18 μm製程之互補式金氧半導體除十二注入鎖定除頻器，此除頻器是由電流型邏輯電路除四除頻器疊接電容交叉耦合式之除三注入鎖定除頻器構成，除十二注入鎖定除頻器在注入訊號強度為0 dBm的情況下有9.49 GHz到9.89 GHz的除頻範圍，其功率消耗為18.21mW。除十二注入鎖定除頻器使用有寬注入鎖定範圍的電流型邏輯電路除四除頻器來跟隨LC注入鎖定除頻器輸出的頻率，此電路的面積為0.927×1.146 mm2。此注入鎖定除頻器還可以當成除二十注入鎖定除頻器和除四注入鎖定除頻器。
第四，本篇設計一個使用了台積電0.18 μm BiCMOS SiGe 製程，此除頻器使用了電耦合和磁耦合來設計LC注入鎖定除頻器。注入鎖定除頻器是由兩個分別工作在3.5 GHz和5.5GHz的單波段LC-tank電容交叉耦合注入鎖定除頻器構成。除二注入鎖定除頻器低頻部分在注入訊號強度為0 dBm的情況下有3.5 GHz到7.2 GHz的除頻範圍，其功率消耗為16.4mW，高頻部分在注入訊號強度為0 dBm的情況下有10.2 GHz到11.8 GHz的除頻範圍，其功率消耗為8.8mW。此電路的面積為0.642×0.996 mm2。
Frequency synthesizer plays an important role of wireless communication system, its blocks include Phase Frequency Detector (PFD), Charge Pump (CP), Loop Filter (LF), Voltage Controlled Oscillator (VCO), and Frequency Divider (FD). In order to pursue low-power, low phase noise and wide Locking range of divider, so this thesis presents the design of high performance Injection-Locked Frequency Dividers (ILFDs).
First, this thesis measures a MOSFET frequency doubler (×2 FD) with negative gate bias to enforce the doubler MOSFET biased in the pinched-off to lower dc power dissipation. The negative gate bias is generated by the HBT diode rectifier using the class-D VCO internal signal as input voltages. The VCO provides peak voltage swing three times of the supply voltage and high negative going voltage. The integrated VCO-FD in the TSMC 0.18 μm BiCMOS uses a silicon die area of 1.1945×1.152 mm2. The varactor-less VCO is tunable by varying the gate bias of the capacitive cross-coupled FETs, so that the frequency doubler output frequency is tunable and it operates from 4.34 GHz to 4.17 GHz. The class-D VCO can be used as a divide-by-2 ILFD by applying a tail injection signal, then the frequency doubler provides a signal with the phase noise and the frequency tracking the injection signal.
Secondly, this thesis measures a CMOS divide-by-16 injection-locked frequency divider (ILFD) with a divide-by-4 current-mode logic (CML) frequency divider (FD) stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-16 ILFD in the TSMC 0.18 μm 1P6M CMOS process has a locking range from 10.81 GHz to 12.82 GHz at the power consumption of 16.05mW and an external injected signal power Pinj of 0 dBm. The varactor-less divide-by-16 ILFD uses the CML FD with wide locking range to track the input frequency from the LC ILFD output, and occupies a small area of 1.2×1.198 mm2. The ILFD also can operate in the divide-by-8 and divide-by-24 modes.
Thirdly, this thesis measures a CMOS divide-by-12 injection-locked frequency divider (ILFD) with a divide-by-4 current-mode logic (CML) stacked on a capacitive cross-coupled oscillator used as an LC divide-by-3 ILFD. The divide-by-12 ILFD in the TSMC 0.18 μm 1P6M CMOS process has a locking range from 9.49 GHz to 9.89 GHz at the power consumption of 18.21 mW and an external injected signal power Pinj of 0 dBm. The varactor-less divide-by-12 ILFD uses the CML FD with wide locking range to track the input frequency from the LC ILFD output, and occupies a small area of 0.927×1.146 mm2.
Finally, this thesis designs technique of using hybrid electric and magnetic coupling to design LC injection-locked frequency dividers (ILFDs). The ILFD uses two single-band LC-tank capacitive cross-coupled sub-ILFDs operating at 3.5 GHz and 5.5 GHz respectively. The divide-by-2 ILFD in the TSMC 0.18 μm BiCMOS uses a silicon die area of 0.642×0.996 mm2.
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