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研究生: 鄭旌甫
Jing-Fu Jheng
論文名稱: 一種用於低功率網路晶片的自適應小型查表路由演算法
An Adaptive Routing Algorithm Using Small Lookup Table for Low Power NoCs
指導教授: 阮聖彰
Shanq-Jang Ruan
口試委員: 林銘波
Ming-Bo Lin
陳維美
Wei-Mei Chen
許孟超
Mon-Chau Shie
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 42
中文關鍵詞: 晶片網路低功率路由演算法
外文關鍵詞: Network-on-chip (NoC), low power, routing algorithm
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  • 晶片網路是一種高效能的傳輸架構,這種平行計算系統被廣泛應用在大型積體電路的設計中,而路由演算法為晶片網路的核心,主宰了整個晶片網路效能的優劣,節點與節點之間的傳輸藉由路由演算法的計算將封包從起始節點分配適當的輸出阜到各個中繼節點,直到達到目的地節點為止,故對於路由演算法的設計而言,如何降低封包平均傳遞時間的延遲是最重要的課題。

    另一方面,雖然我們對於計算機系統的效能、流量、以及速度之需求日益增加,而功率消耗與面積也是我們必須考量的重點。為了解決路由矩陣的問題,一種排列組合樹方法被提出來用於建立封包的路徑,但此種方法需要運算非常多種路由情況,所以基於此種方法上,我們提出了一個只需簡單運算的低功率路由演算法,同時能夠在封包傳輸時運算出最佳的封包路徑。

    在固定或不同的封包流量下,實驗結果皆顯示我們路由演算法相較於排列展開樹演算法有較佳的效能表現,由於利用簡單數學運算做決策的關係也達到節省面積與節省功率消耗的效果。


    Network-on-chip (NoC) architecture is a high performance communication framework. It has been widely used for the hardware design with large-scale chips. Routing algorithm is one of the critical designs in the NoC architecture. For the quality maintenance of the communication between nodes, packets are forwarded from a source node to a destination node in the NoC. The design of routing system is very necessary to suppress the average latency of packets. On the other hand, it is also significant as power and area are both considered for the packet switched on-chip network. To deal with the values of the routing matrix, a permutation tree is used to construct the datapath. With the branches of the tree, there are too many cases of routing decisions to be computed. Based on the scheme, we developed an algorithm which only uses simple arithmetic of operations in order to achieve low power design. This adaptive routing algorithm also select the best route for communication flows. Experimental results show that the performance of our algorithm is better than the routing algorithm with permutation tree under uniform and transpose traffic. Furthermore, the proposed algorithm is also more energy-efficient and area-economic, while the power consumption is much lower than the compared circuit with larger chip area.

    Recommendation Form i Committee Form ii Chinese Abstract iii English Abstract iv Acknowledgements v Table of Contents vi List of Tables ix List of Figures x Table of Algorithms xii 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 System Communication . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Improvement of Communications . . . . . . . . . . . . . . . . . . . . . 3 1.3 NoC Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Basis of NoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 6 2.2 Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 NoC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Circuit Switching . . . . . . . . . . . . . . . . . .. . . . . .. . . . 11 3.2 Packet Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 Virtual Cut-Through Switching . . . . . . . . . . . . . . . . . .. .. . 14 3.4 Wormhole Switching . . . . . . . . . . . . . . . . . . . . . . . . .. . 15 3.5 Bufferless Switching . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Routing Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 XY Routing . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. 17 4.2 Pipelined XY Routing . . . . . . . . . . . . .. . . . . . . . . . . . . 19 4.3 Permutation Tree Routing . . . . . . . . . . . . . . . . . . . . .. . 21 5 Proposed Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 Packet Address . . . . . . . .. . . . . . . . . . . . . . . .. . . . . 25 5.2 Reference Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.3 I/O Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.4 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.1 Packet Latency . . . . . .. . . . . . . . . . . . . . . . . . . . . . . 30 6.2 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.3 Chip Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 32 7 Chip Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Copyright Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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