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研究生: 王彥文
Yen-wen Wang
論文名稱: 可重組態三維系統之熱感知工作管理
Thermal-aware Task Management in Three-dimensional Dynamically Partially Reconfigurable Systems
指導教授: 陳雅淑
Ya-shu Chen
口試委員: 陳筱青
Hsiao-Chin Chen
羅習五
Shi-Wu Lo
謝仁偉
Jen-Wei Hsieh
學位類別: 碩士
Master
系所名稱: 電資學院 - 電機工程系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 100
語文別: 英文
論文頁數: 38
中文關鍵詞: 熱管理可重組態三維現場可程式邏輯閘陣列
外文關鍵詞: dynamically partially reconfigurable, Thermal management, 3D FPGAs
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  • 在三維(3D)可重組態架構(dynamically partial reconfiguration)中,熱管理是一項重要的議題。不同於一般的三維晶片,由於任務再重新配置時會帶來多餘熱的代價(overhead)使在三維可重組態架構的熱管理變得更困難。本論文中提出了一個熱感知任務管理方法,透過搬移低功率任務與高功率任務防止系統溫度過熱,並提出可配置熱門檻(thermal threshold)去平衡重新配置的代價與熱的分布。此熱感知任務管理不僅可提供任務的品質保證,並藉由接受高功率任務最大化系統效能。


    Thermal management is a critical issue in three-dimensional dynamically partially reconfigurable systems.
    Different from three-dimensional integrated circuits, the thermal management is more difficult in
    three-dimensional dynamically partially reconfigurable systems because of the extra thermal generated
    by task reallocation. This study proposes a thermal-aware task management to reclaim the run-time thermal slack from tasks with low powers, and the configurable thermal threshold is used to trade-off the reconfiguration overhead and thermal distribution. The presented task management framework provides the quality of service guarantee under thermal constraints and maximizes the tolerable task power for better utilize the system. The capability of the proposed methodology is evaluated by a series of experiments, for which encouraging results are presented.

    [1] XILINX, http://www.xilinx.com/, 7 Series FPGAs Packaging and Pinout, 2012.
    [2] S. Liu, R. N. Pittman, A. Forin, and J.-L. Gaudiot, “On energy efficiency of reconfigurable systems with run-time partial reconfiguration,” pp. 265–272, Application-specific Systems Architectures and Processors, July 2010.
    [3] J. Resano, D. Mozos, D. Verkest, S. Vernalde, and F. Catthoor, “Run-time minimization of reconfiguration overhead in dynamically reconfigurable systems,” in Signal Processing Systems (SIPS), pp. 585–594, Springer Berlin Heidelberg, September 2003.
    [4] P.-A. Hsiung, C.-H. Huang, J.-S. Shen, and C.-C. Chiang, “Scheduling and placement of hardware/ software real-time relocatable tasks in dynamically partially reconfigurable systems,” ACM Transactions on Reconfigurable Technology and Systems, vol. 4, December 2010.
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    [6] Walder.H., Platzner.M., and Thiele.L, “Online scheduling and placement of real-time tasks to partially reconfigurable devices,” pp. 224–225, Real-Time Systems Symposium, 2003. RTSS 2003. 24th IEEE, December 2003.
    [7] A.Montone,M. D. Santambrogio, F. Redaelli, and D. Sciuto, “Floorplacement for partial reconfigurable fpga-based systems,” International Journal of Reconfigurable Computing, vol. 2011, January 2011.
    [8] P. Banerjee, M. Sangtani, and S. Sur-Kolay, “Floorplanning for partially reconfigurable fpgas,” Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 8–17, January 2011.
    [9] M. Lin, A. E. Gamal, Y.-C. Lu, and S. Wong, “Performance benefits of monolithically stacked 3-d fpga,” Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 216–229, February 2007.
    [10] K. Siozios and D. Soudris, “A novel algorithm for temperature-aware placement and routing on 3d fpgas,” Proc. International Conference on VLSI and System-on-Chip, 2008.
    [11] J. Li, M. Qiu, J. Hu, and E. H.-M. Sha, “Thermal-aware rotation scheduling for 3d multi-core with timing constraint,” pp. 323–326, Field Programmable Logic and Application, October 2010.

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