晶片散熱所產生的『熱』效應(Thermal Effect)是最近幾年來低功率晶片的設計者最想要改善的項目之一，特別是在可攜系統應用產品Notebook、Cell Phone 和PDA。在輕薄短小的電子產品空間內，晶片上產生的熱(Thermal)對系統的功率消耗(Power) 、時序(Timing) 、 效能(Performance)、和可靠度(Reliability)是非常重要的因素。本文是依據晶片產生之熱效應會對洩漏電流功耗(Leakage Power)及RF效能的關係來做為研究主題。在本論文的實驗，我們量測Wi-Fi Skype Phone 整體系統功率消耗，實驗用三種不同環境溫度(-20℃ ,25℃,50℃)來執行:Wi-Fi connect, talk, disconnect, idle, 及RF功率傳輸的效能。本文指出了晶片上的熱與深睡模式消耗功率交互作用下，對延長電池的待機時間是有影響。由實驗結果顯示，系統在低溫環境下，深睡模式的功率消耗是最低(1.3mW) 及RF傳輸功率(14.4dBm)的效能是最高，系統另在高溫環境下，深睡模式的功率消耗則會最高(1.51 mW )及RF傳輸功率(13.6dBm)的效能反而最低。這是由於CMOS電晶體的飽和速度及載子移動率，易受環境溫度高低的影響，導致傳導率的變化，進而影響RF傳輸功率的效能及漏電流。系統如從高溫環境下直接轉至低溫下時，則在深睡模式(Deep Sleep Mode)的功耗下，將會節省17 個百分比的功率消耗，並且延長了電池的待機時間

In recent years, thermal effect generated from the VLSI chip has been one of the items that low power designers want to improve the most, particularly that from the chips in various portable applications, like notebook, cell phone and PDA. In smaller and faster electronic products, thermal effect of VLSI chip is a critical factor to power, timing, performance and reliability as well . How to analyze thermal effect and how to improve power and RF performance of VLSI chip are both the most important issues to all the low power designers. The theme of this essay is to study the relation between thermal effect and leakage power and RF performance. In our experiment, we measured the power consumption of Wi-Fi Skype phone step by step: Wi-Fi connect, talk, disconnect, Idle, and RF Tx power performance under three different environment temperatures (-20℃, 25℃, 50℃). We would like to point out that under the reactive result made happen between thermal effect and deep sleep mode power, idle time can be saved to extend Battery lifetime. Based on the result of the experiment, the deep sleep mode in low power is the lowest (1.3 mW) power consumption and RF Tx power performance is the highest value (14.4dBm) under low temperature environment. But the deep sleep mode in low power is the highest (1.51 mW) power consumption, and RF Tx power performance is the lowest value (13.6dBm) under high temperature environment. This is due to that the characteristic of CMOS is easily to be affected by the temperature around, which caused the change of RF performance and the leakage of system chip. The paper is concluded that when the environment temperature changes from high to low, 17 percentage of power consumption can be saved under deep sleep mode of Wi-Fi power consumption, and the battery lifetime is extended in idle mode of Wi-Fi Skype phone.

[1] Arman Vassighi , Manoj Sachdev ," Thermal and Power management of integrated circuits ". Springer Press, 2005.
[2] A. P. Chandrakasan and R. W. Brodersen, " Statistical analysis and Optimization for VLSI: Timing and Power ". Springer Press, 2005.
[3]Massoud Pedram, Shahin Nazarian. "Thermal Modeling, Analysis, and Management in VLSI Circuits: Principles and Methods ". Proceedings of the IEEE Vol. 94, No. 8, August 2006.
[4] Scott Thompson, Paul Packan, and M.bohr," MOS Scaling: Transistor Challenges for the 21st Century". Intel Technology Journal ,Q3, Page 1-19,1998.
[5] M. Marz, P. Nance , "Thermal modeling of Power-electronic Systems ". Infineon Technologies, AG, Munich.
[6] A. Keshavarzi, K. Roy and C.F. Hawkins. "Intrinsic leakage in deep submicron CMOS ICs: measurement based test solutions". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 6, pages 7 l7-723,2000.
[7] Kiat-Seng. Yeo, Samir S. Rofail and Wang –Ling Goh, "CMOS/BiCMOS ULSI –low Voltage, Low Power " Prentice Hall Press ,2002.
[8] Sung-Mo Kang, Yusuf Leblebici. "CMOS Digital integrated Circuit –Analysis and Design " .McGraw Hill Press ,2002.
[9] Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, "Low-Power CMOS Digital Design ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, No. 6, pages 7 l7-723,2000.
[10] T. Sakurai , H. Kawaguchi , T. Kuroda. "Low-power CMOS design through VTH control and low-swing circuits". Proceedings of the international symposium on Low power electronics and design, pages 1- 6, 1997.
[11] H. Sanchez, B. Kuttanna, T.Olson, M.Alexander, G.gerosa, R.Philip,and J.Alvarez ." Thermal management system for high performance PowerPC microprocessor" Proceedings of IEEE COMPCON,pages 325-330,1997.
[12] N. Sirisantana, L. Wei and K. Roy. "High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness". Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors, pages 227-232,2000.
[13] A. Vassighi,O.Semenov, and M.Sachdev,"Thermal Runaway Avoidance" ,IEEE International Reliability Physics Symposium,pages 655-656,2004
[14] William F. Clark, Member, Badih El-Kareh, , Renato G. Pires,,Stephen L. Titcomb, , and Richard L. Anderson, "Low Temperature CMOS –A Brief Review". IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. 15, NO. 3, JUNE 1992
[15] S. Narendra, S. Borkar, V. De, D. Antoniadis, and A. Chandrakasan, "Scaling of stack effect and its application for leakage reduction". Proceedings of International Symposium of Low Power Electronics and Design (ISLPED), pages 195-200,2001. 4 6 Thermal and Power Management of Integrated Circuits.
[16] William F. Clark, Badih El-Kareh, Renato G. Pires, Stephen L. Titcomb, and Richard L. Anderson, " Low Temperature CMOS-A Brief Review ". IEEE Transactions on Components, hybrids, and manufacturing technology .3 ,June 1992.
[17] T.J.Goh,A.N. Amir, C.P.Chiu, and J. Torresola. "Novel thermal validation metrology based on non-uniform power distribution for Pentium I11 Xeon cartridge processor design with integrated level two cache". Proceedings of Electronic Components and Technology Conference, pages 18 - 186, 2001.
[18] S.H. Gunter, F. Binns, D.M. Carmean, and J.C. Hall. "Managing the impact of increasing microprocessor power consumption". Intel Tech.Journal, Q 1 : 1-9,2001.
[19] Accton Coperation ,http://www.accton.com.tw/ .
[20] TI OMAP http://www.ti.com/OMAP .
[21] R. Viswanath, V. Wakharkar, A. Watwe, and V. Lebonheur. "Thermal performance challenges from silicon to systems". Intel Technology Journal, Q3, pages 1-16,2000.
[22] P. Tadayon. "Thermal challenges during microprocessor testing". Intel Technology Journal, Q3, pages 1-8,2000.
[23] R.C. Joy and E.S. Schlig. "Thermal properties of very fast transistors".IEEE Transaction on Electron Devices, ED-Vol. 17, No. 8, pages 586- 594, 1970.
[24] S.Lee ,D.J.Allstot, " Electro-thermal simulation of integrated circuits". IEEE Journal of Solid-state Electronics, SSC-Vol.28,No.12,page 1283-1293,1933
[25] S.Wunsche,C.Clause,P.Schwarz,F.Winkler, "Electro-thermal circuit simulation using simulator coupling "IEEE Transaction on Very Large Scale integration(VLSI) System ,Volume 5,Issue 3, pages 277- 282, 1970.
[26]W.vanPETEGEM,b.Geeraeerts,W.Sansen,B.graindourze "Electro thermal simulation and design of integrated circuits". IEEE Journal of Solid-state Electronics, Volume 29 ,Issue 2,page 143-146,1994
[27] A.Keshavarzi,k.Roy and C.F. Hawkins. “Intrinsic Leakage in deep submicron CMOS ICs: measurement based test solutions”, IEEE transactions on Very large scale integration(VLSI) Systems,Vol.8 ,No.6,Pages 717-723,2000
[28]J.P. Halter,and F.N. Najm, “ A gate-level leakage power reduction method for ultra-low power CMOS Circuit ”,Proceedings of the IEEE CICC, Page 475-478.1977
[29] J.Srinivasan and S.V.Adve. “Predicive dynamic thermal management for multimedia application ”,in Proc. 17th Annu.Int.Conf. Supercomputing ,2003,
[30] D. Brooks and M. Martonosi, B“ Dynamic thermal management for high-performance microprocessors”, in Proc. Int. Symp.High-Performance Computer Architecture, 2001,pp. 171–182.[79] D. Brooks, V. Tiwari, and M. Martonosi,
[31] H. Chiueh, J. Draper, and J. Choma, Jr.,B “ A dynamic thermal management circuit for system-on-chip design“,J. Analog Integr.Circuits Signal Process., vol. 36, no. 1–2,pp. 175–181, Jul.–Aug. 2003.
[32] K.Banerjee, A.Mehrotra, A.Sangiovanni-Vincentelli, and C.Hu, “ On thermal effects in deep sub-micron VLSI interconnects“ ,in Proc. Design Automation Conf.,1999,pp.885-891
[33] Wei Huang,Shougata Ghosh, Siva Velusamy, Karthik Sankaranarayanan,Kevin Skadron, and Mircea R. Stan, “HotSpot: A Compact Thermal Modeling Methodology for Early-Stage VLSI Design “ , IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 5, MAY 2006
[34]魏子茵, “研新三路“,智邦科技內部季刊,VOL 1,NO.3 pp.14-17, Dec.2006