奇異值分解在各種訊號處理的應用領域中扮演著非常重要的角色，因此多年來諸多學者提出各種高效能的演算法與電路架構進行奇異值分解運算。然而，絕大多數文獻中提出的奇異質分解演算法或電路架構皆假設矩陣為一方陣。由於許多應用都需要對任意大小矩陣進行奇異值分解運算，假設矩陣為一方陣極大限制了這些運算方法的實用性。本論文提出了一種高處理速度高硬體利用率之奇異值分解處理器，並且能夠對任意大小矩陣進行奇異值分解運算，以滿足對任意大小矩陣分解的需求。具體而言，本論文提出了一種新的奇異質分解演算法，以降低傳統演算法的迭代次數，使得處理速度得到顯著提升。同時，本論文設計的電路架構是基於分時多工的運算流程方法，以達到提升了計算單元的硬體使用率，更進一步提升處理速度與效率。本文所提出之奇異值分解處理器是基於積體電路設計流程並採用CMOS 90 奈米製程來實現，其效能評估採用自動化布局與繞線後的結果。實驗結果表示，我的設計的電路複雜度以NAND 邏輯閘來估計約為210.64k 個，而處理效能達到每秒15384.6k 個矩陣運算的處理速度。相較於先前文獻的設計，本文所提出的奇異值分解處理器在方正矩陣的情況下，效能提升了約25.3%，而在非方正矩陣的情況下，效能提升了約33.1%。

Singular value decomposition (SVD) plays an essential role in the field of signal processing applications. Therefore, many scholars over the years propose various high-efficiency algorithms and circuit architectures for singular value decomposition operations. However, most of the literature proposes both the singular value decomposition algorithm and the circuit structure for a square matrix. Since many applications require singular value decomposition operation of the matrix with an arbitrary size, assuming that the matrix is square greatly limits the practicability of these approaches. This thesis presents a singular value decomposition processor with high throughput and high hardware utilization. Furthermore, the design proposed in this work can decompose matrices of any size and meet the needs of arbitrary matrix decomposition. Specifically, a novel algorithm is presented in this thesis where the number of iterations is greatly reduced so that the processing throughput can be significantly enhanced. Moreover, the utilization rate of the computing hardware units is improved by means of the carefully designed processing flow. This further improves the throughput rate and efficiency. The proposed SVD processor is designed and implemented using the design process of application-specific integrated circuit (ASIC) with CMOS 90nm technology. The performance is estimated by the results of automatic placement and routing. The experimental results demonstrate that the complexity of the proposed design is 210.64k represented by logic NAND gates. It is also shown in this thesis that the maximum throughput is up to 15384.6k matrices per second. Compared with the previous literature on singular value decomposition, the efficiency of square matrices and non-square matrices of SVD is higher about 25.3% and 33.1%.

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