本論文中提出了一個基於快速二補數運算的低功率高效能二補
數產生器晶片，利用較省面積的CMOS電晶體組成快速運算架構，
並使用快速找1的方法，來達成快速二補數的轉換。並且依據二補數
算術演算法實現低功率二補數產生器，可以廣泛地應用在許多數位
濾波器上。為了能夠有效節省面積，我們使用快速找1之CMOS電晶
體架構運算，再依多工器架構選擇出正確的二補數值。
在此電路設計中，更進一步改進了兩個缺點：在傳統二補數電
路中，是利用「反相加1」的運算方式，因此應用到許多的邏輯閘，
所以消耗功率非常高 ; 除此之外，相較於快速找1之OR-XOR電路
中，消耗功率雖有降低，但硬體面積卻會隨著輸入位元長度增加而
增加，因此我們設計快速找1之CMOS電路，不僅可以有效降低功率，
也能減少硬體的複雜度與面積，並且還避免了不必要的傳遞延遲。
晶片的電路功能驗證正確後，再測量晶片功率消耗，並且與其
它二補數電路相比，此實作電路達到67%的功率改善，並且面積也
減少了68%。

In this thesis, a low-power high-performance two's complement generator chip design based on fast-finding one approach (FFO) operation is proposed. It achieves high-
speed with fewer CMOS transistors to reduce area, and to achieve rapid conversion of the two's complement arithmetic. Many digital filters are widely implemented in
hardware using two's complement arithmetic. In order to effectively reduce the area, this thesis proposes a CMOS transistor architecture with the FFO operation which
utilizes a multiplexer architecture to select the correct two's complement value.

The proposed architecture further improves the following two drawbacks. One is that the conventional two's complement circuit is designed by inversion-add-one
scheme which results in high power consumption by using high amount of logic gates. The other is that in the OR-XOR circuit, the FFO approach has lowed power consumption, and the length of the input bit increases proportionally with the hardware area; therefore, the proposed implementation with the FFO approach not only reduces the area of the circuit but also improves the power consumption. In addition, the proposed method avoids the non-negligible propagation delay.

Circuit validation of the chip shows that the proposed scheme achieves not only at least 67% power improvement but also 68% circuit area reduction with significant performance improvement comparing to the conventional one.

[1] Y. Kim and L.-S. Kim, "A low power carry select adder with reduced area," in
Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on, vol. 4, May 2001, pp. 218-221 vol. 4.
[2] J. Dobson and G. Blair, "Fast two's complement vlsi adder design," Electronics Letters, vol. 31, no. 20, pp. 1721-1722, Sep 1995.
[3] H. Srinivas and K. Parhi, "A fast vlsi adder architecture," Solid-State Circuits, IEEE Journal of, vol. 27, no. 5, pp. 761-767, May 1992.
[4] X. Li, X. Yu, C. Wang, and B. W.-K. Ling, "Periodic input response of a second-order digital filter with twos complement arithmetic," Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 56, no. 10.1109/TCSII, pp. 225-229, March 2009.
[5] B. Ling, C.-F. Ho, and P.-S. Tam, "Nonlinear behaviors of first and second-order complex digital filters with two's complement arithmetic," Signal Processing, IEEE Transactions on, vol. 54, no. 10, pp. 4052-4055, Oct. 2006.
[6] B. W.-K. Ling, W.-F. Hung, and P. K.-S. Tam, "Chaotic behaviours of
stable second-order digital filters with two's complement arithmetic," International Journal of Circuit Theory and Applications, vol. 31, pp. 541-554, 2003.
[7] J. Valls and E. Boemo, "Efficient fpga-implementation of two's complement digit-serial/parallel multipliers," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 50, no. 6, pp. 317-322, June 2003.
[8] P. Bhansali, K. Hosseini, and M. Kennedy, "Performance analysis of low
power high speed pipelined adders for digital sigma delta modulators,"
Electronics Letters, vol. 42, no. 25, pp. 1442-1444, 2006. [Online]. Available:
http://link.aip.org/link/?ELL/42/1442/1
[9] M. A. Karim and X. Chen, Digital Design: Basic Concepts and Principles, 1st ed. Boca Raton, FL, USA: CRC Press, Inc., 2007.
[10] D. Patterson and J. Hennessy, Computer Organization and Design: The Hard-
ware/software Interface. Morgan Kaufmann, 2005.
[11] M. M. Mano and C. R. Kime, Logic and computer design fundamentals. Prentice
Hall, 2007.