在無線通訊系統中，頻率合成器是用來做訊號頻率的升降之用。在頻率合成器電路裡，壓控振盪器與除頻器是重要的核心電路之ㄧ。對壓控振盪器而言，必須提供低相位雜訊的輸出，以避免相鄰雜訊訊號經由混波轉換產生干擾。而振盪器的輸出則經由除頻器來達成降頻的工作，因此，除頻器需具有高頻操作、寬的操作頻寬及低功率消耗。

在第一部分，呈現一個使用五個電感雙頻帶之除四注入鎖定除頻器，電路主要架構為一個使用N型金氧半電晶體的交錯偶合對之壓控震盪器，共振腔由五個電感組成，加上一個並聯於共振腔用於注入訊號之N型金氧半電晶體，此晶片使用台積電矽鍺0.18微米製程，晶片面積為0.865 ×0.872 mm2，在交錯偶合對之閘極偏壓可控制電路的功耗，並在頻率鎖定範圍與電路功耗大小之間作取捨找出最佳偏壓點為0.7 V，此電路工作電壓為1.1 V，整體功耗為10.34 mW，再注入訊號功率0 dBm之除四鎖定頻率範圍為9.8~14.5 GHz，百分比為38.68 %。

第二部分，介紹一個雙主頻率同時震盪之壓控震盪器，晶片使用台積電矽鍺0.18微米製程，晶片面積為1.057 ×1.071 mm2，電路主要架構部分使用兩個壓控震盪器，並透過LC電路作耦合，共振腔電路使用兩個右手LC震盪電路，透過使用N型金氧半電晶體之交錯耦合對最為負阻抗，補償共振腔電路之損耗，改變共振腔電路可變電容之容值可使電路震盪頻率升降，電路供應電壓0.8 V，電路震盪於3.79 GHz時功耗為3.43 mW，相位雜訊在1 MHz時為-121.04 dBc/Hz，FOM為-187.1 dBc/Hz，當電路震盪於高頻帶，震盪頻率為6.03 GHz，功耗1.63 mW，相位雜訊在1 MHz時為-116.99 dBc/Hz，FOM為-190.2 dBc/Hz。

第三部分，介紹一個可切換之雙主頻率同時震盪壓控震盪器，電路主要架構為兩個N型金氧半電晶體之交錯耦合對使用串聯可調之LC共振腔，改變共振腔之可變電容容值大小可使電路震盪於高頻或低頻，透過改變控制電流之HBT基極偏壓，可使電路出現雙主頻率震盪之現象，電路供應電壓為0.7 V，電路功耗2.6 mW，高頻/低頻FOM為-192/-190 dBc/Hz，晶片使用台積電矽鍺0.18微米製程，晶片面積為1.04 ×0.55 mm2 。

In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal by close interfering tones. The output of the VCO is divided down by the frequency divider which requires operating at high frequencies, wide operating range and lower power consumption.

In chapter 4, we present a wide locking range divide by four injection lock frequency divider using five on chip inductors. The ILFD using a cross coupled voltage-controlled oscillator (VCO) with one direct injection MOSFET. The resonator using five on chip inductors. The chip was implemented in the tsmc 0.18 μm SiGe 3P6M BiCMOS process. The die area is 0.865 ×0.872 mm2. The dc gate bias of cross coupled FETs can be tuned for the tradeoff between locking range and power consumption. The core power consumption is 10.34 mW at supply voltage 1.1 V. At the incident power of 0 dBm the locking range is 4.7 GHz (38.68%) from 9.8 to 14.5 GHz.

In chapter 5, we present a voltage controlled concurrent oscillator. The chip was implemented in the tsmc 0.18 lm SiGe 3P6M BiCMOS process. The die area is 1.057 ×1.071 mm2. The concurrent oscillator using two VCOs coupled by an LC network. The VCO uses two units of right-handed (RH) LC resonator stacked in series, and the LC resonator is in shunt with a pair of cross-coupled transistors to compensate the loss of LC resonator. The supply voltage is 0.8 V. The high band oscillation frequency is 3.79 GHz and the power consumption is 3.43 mW. The phase noise at 1MHz frequency offset is -121.04 dBc/Hz, and FOM is -187.1 dBc/Hz. The low band oscillation frequency is 6.03 GHz and the power consumption is 1.63 mW. The phase noise at 1MHz frequency offset is -116.99 dBc/Hz, and FOM is -190.2 dBc/Hz.

In chapter 6, we present a concurrent oscillator with switching mode. The oscillator consists of two cross-coupled BiCMOS oscillators with shared series-tuned LC-tank. The series-tuned LC-tank plays the role in the oscillation frequency. By varying the tail transistor the concurrent oscillation occurs. The power consumption is 2.6 mW at supply voltage 0.7 V. The chip was implemented in the tsmc 0.18 lm SiGe 3P6M BiCMOS process. The die area is 1.04 ×0.55 mm2.

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