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研究生： 賴威志
Wei-Chih Lai
論文名稱： 超寬鎖頻範圍之除五注入鎖定除頻器與寬鎖頻範圍之除四注入鎖定除頻器之設計
Design of An Ultra Wide-Band Divide-by-5 Injection-Locked Frequency Divider and A Wide-Band Divide-by-4 Injection-Locked Frequency Divider Using Resonator
指導教授： 張勝良
Sheng-Lyang Jang
莊敏宏
Miin-Horng Juang
口試委員: 徐世祥
Shih-Hsiang Hsu
徐敬文
Ching-Wen Hsue
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2015
畢業學年度： 103
語文別： 英文
論文頁數： 92
中文關鍵詞： 壓控震盪器 、注入鎖定除頻器
外文關鍵詞： VCO, ILFD
相關次數： 點閱：156  下載：3 
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    • 本論文提出三個電路，第一個電路先描述一個超寬鎖頻範圍除五注入鎖定除頻器，是使用 TSMC 0.18 μm CMOS製程。此注入鎖定除頻器是使用雙諧振RLC共振腔以及線性混波器來擴展鎖頻範圍。量測結果為供應電壓1.15 V，而高頻和低頻是藉由偏壓改變可變電容容值,造成頻率改變分別在3.10和2.81 GHz，核心功耗為8.38 mW。注入訊號為0 dBm時，其除五鎖頻範圍為11.4至15.8 GHz (32.35%)。
    第二個電路描述一個除五寬鎖頻範圍單端注入鎖定除頻器，此電路是使用TSMC 0.18 μm CMOS製程所實現，量測結果為供應電壓1.15 V，而可調範圍則是使用電壓來改變可變電容，達到頻率可調的機制。可調範圍由2.81 GHz至3.10 GHz，當注入訊號功率為0 dBm時，其總鎖頻範圍為12.8 GHz至15.6 GHz (19.7%)，總功耗為8.38 mW。
    最後一個電路是描述一個除四寬鎖頻範圍注入鎖定除頻器，是使用TSMC 0.18 μm CMOS製程。此注入鎖定除頻器是使用雙諧振RLC共振腔以及線性混波器來擴展鎖頻範圍。量測結果為供應電壓1.4 V，核心功耗為11.872 mW。可調範圍則是使用電壓來改變可變電容，達到頻率可調的機制,可調範圍由2.69 GHz至2.87 GHz。注入訊號為0 dBm時，其除四鎖頻範圍為9.5至12.7 GHz (28.82%)。

    Firstly, this thesis presents an ultra wide locking range divide-by-5 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process . The ILFD circuit is realized with a cross-coupled n-core MOS dual-resonance RLC-tank oscillator with linear mixer to extend the locking range. The core power consumption of the ILFD core is 8.38 mW. The divider’s free-running frequency has dual-bands at 3.10 and 2.81 GHz by switching the varactor’s control bias, At the incident power of 0 dBm, the locking range is 4.4 GHz (32.35%), for the incident frequency extending from 11.4 to 15.8 GHz.
    The second circuit is a wide locking range divide-by-5 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process . The ILFD circuit is realized with a capacitive cross-coupled n-core MOS dual-resonance RLC-tank oscillator with linear mixer to extend the locking range. The core power consumption of the ILFD core is 8.38 mW. The ILFD uses a single injection MOSFET. At the incident power of 0 dBm, the locking range is 2.8 GHz (19.7%) for the incident frequency extending from 12.8 to 15.6 GHz.
    Finally, an ultra wide locking range divide-by-4 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD circuit is realized with a cross-coupled n-core MOS dual-resonance RLC-tank oscillator with linear mixer to extend the locking range. The core power consumption of the ILFD core is 11.872 mW. The divider’s free-running frequency has dual-bands at 2.87 and 2.69 GHz by switching the varactor’s control bias, At the incident power of 0 dBm the locking range is 3.2 GHz (28.82%), for the incident frequency extending from 9.5 to 12.7GHz.

    List of Contents 中文摘要 I Abstract III 誌謝 V List of Contents VI List of Figures VIII List of Tables XII Chapter 1 Introduction 1 1.1 BACKGROUND 1 1.2 THESIS ORGANIZATION 4 Chapter 2 Design of Voltage Controlled Oscillators 6 2.1 INTRODUCTION 6 2.2 BASIC THEORY OF OSCILLATOR 7 2.2.1 FEEDBACK(TWO-PORT) OSCILLATORS 8 2.2.2 NEGATIVE RESISTANCE 11 2.3 QUALALITY FACTOR 13 2.4 SORTS OF OSCILLATORS 14 2.4.1 RESONATORLESS OSCILLATORS 15 I. RING OSCILLATOR 15 II. RELAXATION OSCILLATOR 17 2.4.2 LC-TANK OSCILLATORS 18 I. COLPITTS AND HARTLEY OSCILLATORS 18 II. NEGATIVE -GM OSCILLATORS 19 2.5 VARACTORS 21 2.5.1 JUNCTION VARACTORS 21 2.5.2 MOS VARACTORS 21 I. INVERSION-MODE PMOS VARACTOR (I-MOS) 23 II. ACCUMULATION-MODE PMOS VARACTOR (A-MOS) 24 2.6 INDUCTOR AND TRANSFORMERS 24 2.6.1 SPIRAL INDUCTOR 25 2.6.2 THE TRANSFORMER 31 2.7 DESIGN CONCEPTS OF VCO 36 2.7.1 VCO CHARACTERISTIC PARAMETERS 37 2.8 APPEARANCE OF DUAL-RESONANCE 44 2.8.1 DUAL-BAND RESONATOR 44 2.8.2 TWO SERIES-LC RESONATORS 49 2.9 INJECTION LOCKING FREQUENCY DIVIDER 50 2.9.1 PRINCIPLE OF INJECTION LOCKED FREQUENCY DIVIDER 51 2.9.2 LOCKING RANGE 53 2.9.3 SWITCH ILFD 56 Chapter 3 An Ultra Wide-Band Divide-by-5 Injection-Locked Frequency Divider 58 3.1 INTRODUCTION 58 3.2 CIRCUIT DESIGN 60 3.3 MEASUREMENT RESULTS 63 Chapter 4 A Wide Locking Range Divide-by-5 Injection-Locked Frequency Divider Using Single Injection MOSFET 69 4.1 INTRODUCTION 69 4.2 CIRCUIT DESIGN 70 4.3 MEASUREMENT RESULTS 71 Chapter 5 A Wide Locking Range Divide-by-4 Injection-Locked Frequency Divider Using RLC Resonator 77 5.1 INTRODUCTION 77 5.2 CIRCUIT DESIGN 79 5.3 MEASUREMENT RESULTS 80 Chapter 6 Conclusion 87 References 89

    References

    [1] N. M. Nguyen and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuit, vol. 27, no. 5, pp. 810–820, May 1992.
    [2] B.Razavi, RF Microelectronics, Prentice Hall PTR 1998.
    [3] B. Razavi, “A study of phase noise in CMOS oscillators, ” IEEE J. Solid-State Circuits, vol. 31, p.p. 331-343 Mar. 1996.
    [4] K. Shu, E. Sanchez-Sinencio, CMOS PLL Synthesizers : Analysis and Design, Springer, 2005.
    [5] A. Porret, T. Melly, C. Enz, and E, Vittoz, “Design of high-Q varactors for low-power wireless applications using a standard CMOS process,” IEEE J. Solid-State Circuits, vol. 35, pp. 337-345, Mar. 2000.
    [6] F. Svelto, P. Erratico, S. Manzini, and R. Castello, “A metal oxide semiconductor varactor,” IEEE Electron Device Lett., vol. 20, pp. 164-166, Apr. 1999.
    [7] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCO’s,” IEEE J. Solid-State Circuits, vol. 35, pp. 905-910, Jun. 2000.
    [8] T. Soorapanth, C. Yue, D. Shaeffer, T. Lee, and S. Wong, “Analysis and optimization of accumulation-mode varactor for RF ICs,” in 1998 Symp. VLSI Circuits Dig. Tech. Papers, , pp. 22-23. Jun. 1998.
    [9] J. Aguilera, and R. Berenguer, “Design and test of integrated inductors for RF applications,” Kluwer Academic Publishers, 2004.
    [10] J. Craninckx, and M. S. J. Steyaert, “A fully integrated CMOS DCS-1800 frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, 1998.
    [11] Y. K. Koutsoyannopoulos and Y. Papananos, “Systematic analysis and modeling of integrated inductors and transformers in RF IC design,” IEEE Trans. Circuits and System-II, vol. 47, no. 8, pp. 699-713, 2000.
    [12] A . Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628, Apr. 2001.
    [13] Y. Koutsoyannopoulos, “Novel Si integrated inductor and transformer structure for RF IC design,” Proc. ISCAS , vol. 2, pp. 573-576, June. 1999.
    [14] C. Tang, C. Wu, and S. Liu, “Miniature 3-D inductors in standard CMOS process,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 471-480, 2002
    [15] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Trans. on Parts, Hybrids and Packaging, vol. PHP-10, no.2, pp. 101-109, 1974.
    [16] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE J. Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
    [17] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
    [18] B. Razavi, Design of Analog CMOS Integrated Circuits, Mc Graw Hill, 2001.
    [19] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 um CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, July 1996.
    [20] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
    [21] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
    [22] H. R. Rategh, and T.H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, June 1999.
    [23] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sept. 2002.
    [24] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 um standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
    [25] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
    [26] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, June 2001.
    [27] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An Injection Locking Scheme for Precision Quadrature Generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, July 2002.
    [28] W. Z. Chen, and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25pm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 89-92, Sept. 2002.
    [29] H. Wu, “Signal generation and processing in high-frequency/high-speed silicon- based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
    [30] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
    [31] X. Yi, C. C. Boon, M. A. Do, K. S. Yeo, and W. M. Lim, “Design of ring-oscillator-based injection-locked frequency dividers with single-phase inputs”, IEEE Microw.Wireless Compon. Lett., vol. 21, no. 10, pp. 559-561, 2011.
    [32] J. Jeong and Y. Kwon, “V-band high-order harmonic injection-locked frequency-divider MMICs with wide bandwidth and low-power dissipation,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 1891-1898, Jun. 2005.
    [33] P.-K. Tsai, T.-H. Huang and Y.-H. Pang, “CMOS 40 GHz divide-by-5 injection-locked frequency divider, ” IET Electronics Letters, vol.46, no.14, pp.1003-1004, Jul. 2010.
    [34] M.-W. Li, P.-C. Wang, T.-H. Huang, and H.-R. Chuang, “Low-voltage, wide locking range, millimeter-wave divide-by-5 injection-locked frequency dividers,”IEEE Trans. Microw. Theory Tech., vol. 60, no. 3, pp. 679–685, Mar. 2012.
    [35] M. Jalalifar and G.-S. Byun, ” A K-band divide-by-five injection-locked frequency divider using a near-threshold VCO,” IEEE Microw. Wireless Compon. Lett., vol. 24, no. 12, pp. 881-883, 2014.
    [36] S.-L. Jang, Z.-H. Wu, C.-W. Hsue and H.-F. Teng,” Wide-locking range dual-band injection-locked frequency divider,” Microw. Opt. Technol. Lett. vol. 55, 10, pp. 2333–2337, October 2013.
    [37] S.-L. Jang, L.-Y. Huang, C.-W. Hsue, and J.-F. Huang," Injection-locked frequency divider using injection mixer DC-biased in sub-threshold," IEEE Microw. Wireless Compon. Lett., vol. 25, no. 3, pp. 193-195, March 2015.
    [38] W. Chen, and C. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25μm CMOS Technology” European Solid-State Circuits Conf. pp. 89- 92, Sept. 2002.
    [39] S. H. Lee, S. L. Jang, and Y. H. Chung, “A low voltage divide-by-4injection locked frequency divider with quadrature outputs,” IEEE Microw.Wireless Compon. Lett., vol. 17, no. 5, pp. 373–375, May 2007.
    [40] K. Yamamoto and M. Fujishima, “70 GHz CMOS harmonic injectionlockeddivider,” in IEEE Int. Solid-State Circuits Conf. Dig.,pp. 2472–2481, Feb. 2006.

    [41] S.-L. Jang,C. C. Liuand C.-W. Chung,” A tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol.19,no. 4,pp. 236-238, April 2009.
    [42] Z.-D. Huang, C.-Y. Wu, and B.-C. Huang, “Design of 24-GHz 0.8-V1.51-mW coupling current-mode injection-locked frequency dividerwith wide locking range,” IEEE Trans. Microw. Theory Techn., vol.57, no. 8, pp. 1948–1958, Aug. 2009.
    [43] S.-L. Jang, L.-Y. Tsai and C.-F. Lee, ” A CMOS switched resonator frequency divider tuned by the switch gate bias,” Microwave and Optical Technology Lett.,Vol. 50, no. 1, pp.222-225, Jan. 2008.
    [44] L. Wu and H. C. Luong, ”Analysis and design of a 0.6 V 2.2 mW 58.5-to-72.9 GHz divide-by-4 injection-locked frequency divider with harmonic boosting’, IEEE Trans. Circuits and Systems-Part I, Regular Papers, vol. 60, no. 8, pp. 2001-2008, Nov. 2013.
    [45] Y.-H. Kuo, et al., “Design and analysis of a 77.3% locking-range divide-by-4 frequency divider,”IEEE Trans. Microw. Theory Tech., vol. 59, no. 10, pp. 2477-2485, Oct. 2011.
    [46] A. Musa, K. Okada, and A. Matsuzawa, “Progressive mixing technique to widen the locking range of high division-ratio,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 3, pp. 1161-1173, Mar. 2013.
    [47] S.-L. Jang, C.-H. Liu, C.-W. Chang, and M.-H. Juang," A low voltage, low power divide-by-4 LC-tank injection-locked frequency divider, " Int. J. Electronics., vol. 98,no. 4, pp. 521-527, April 2011.
    [48] M.-C. Chuang, J.-J.Kuo, C.-H.Wang, and H. Wang, ”A 50 GHz divide-by-4 injection lock frequency divider using matching method’, IEEE Microw.Wireless Compon. Lett., vol. 18, pp. 344–346, May 2008.
    [49] S.-L. Jang, and C.-C. Fu. ” Wide locking range divide-by-4 LC-tank injection-locked frequency divider using series-mixers’, Analog Integr Circ Sig Process, vol. 78, issue 2, pp. 523–528, Feb. 2014., Feb. 2014.

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