隨著消費性電子產品迅速地發展，對於儲存裝置的需求也明顯地增加。由於快閃記憶體有存取時間短、高儲存密度和低功率消耗等優點，讓大多數的產品都是使用快閃記憶體來儲存資料或訊息，例如行動電話和固態硬碟等。快閃記憶體是一種由浮閘電晶體所組成的非揮發性記憶體，而且是在浮閘上儲存或移除電子來完成寫入或清除動作。由於半導體製程的縮減，快閃記憶體在良率、可靠度和耐久度上會面臨嚴重的議題。為了克服這些議題，使用錯誤更正碼技術可以修復快閃記憶體的永久性故障與增加耐久度，藉此改善快閃記憶體的製造良率與可靠度。然而，如果一個編碼字的故障細胞數量超過使用的錯誤更正碼技術的修復能力範圍時，這個編碼字就無法被正確地修復。
因此，我們提出基於位址重映射技術之適應性錯誤更正碼技術用來解決這些問題，主要想法為使用在非及型快閃記憶體的頁緩衝器中改變邏輯位址對實體位址的映射關係，使得故障細胞能均勻地分布到不同的編碼字中。根據在產品測試或線上內建自我測試的結果，使用每一個快閃頁的故障位元圖執行位址重映射演算法並且評估控制字。為了執行位址重映射技術，我們也提出一個新型頁緩衝器架構，使用以靜態隨機存取記憶體為主的記憶體陣列，並且將頁緩衝器分割成多個緩衝器站，每一個緩衝器站分別對應一個控制字，我們根據控制字能重新組成編碼字來均勻地分布故障細胞。
我們開發出一個模擬器用來評估快閃記憶體的修復率、硬體成本、有效良率和可靠度。根據實驗的結果，硬體成本幾乎可以忽略。當快閃記憶體中的故障被偵測時，相較於只使用錯誤更正碼技術，使用本篇技術的修復率能維持在 93% 以上。當快閃記憶體的原始良率為 95%，經由修復後的有效良率可以高於 98%。此外，在正常操作下經過 150000 小時後，快閃記憶體的可靠度仍然可以達到 96% 的水準。

With the rapid development of electrical consumer products, the demand of the storage devices keeps increasing rapidly. Flash memory contains many advantages such as low access time, high storage capacity, and low-power consumption, etc. They are widely used for storing data and/or information in mobile phones and solid-state disks (SSD). Flash memories are a type of non-volatile memories based on floating-gate (FG) transistors—storing or removing charges on the FG electrically. With the process being scaled down, flash memory faces many serious issues in yield, reliability, and endurance. In order to conquer these issues, error correction code (ECC) techniques have been widely used for protecting their permanent faults and improving endurance. Therefore, the fabrication yield and reliability can also be enhanced significantly. However, if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC techniques, the codeword cannot be repaired correctly.
Therefore, we propose the adaptive ECC techniques based on address remapping to cure these drawbacks in this thesis. The main idea is that we can change the logical-to-physical address mapping of the page buffer such that the faulty cells can be evenly distributed into different codewords. Based on the production test or on-line BIST results, the fault bitmap of each flash page can be used for executing the address remapping algorithm and evaluating the control words. To conduct the address remapping, a novel page buffer design is also proposed. The page buffer is basically a SRAM-based memory array. We partition it into several buffer banks and each buffer bank contributes one bit for its corresponding control word. Based on the control words, we can reconfigure the codewords to distribute the faulty cells evenly.
A simulator is also developed to evaluate the repair rate, hardware overhead, effective yield, and reliability. According to experimental results, the hardware overhead is negligible. Moreover, the effective yield is higher than 98% by using our technique. The reliability of flash memory can still achieve the level of 96% after 150000 hours of normal operations.

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