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研究生: 巫忠達
Zhong-Da Wu
論文名稱: 針對邊緣運算上卷積神經網路推導之低累加次數的 移位殘差相加布氏乘法器
Accumulation-Aware Shift and Difference-Add Booth Multiplier for Convolutional Neural Networks Inference Targeting on Edge Computing
指導教授: 阮聖彰
Shanq-Jang Ruan
口試委員: 蔡宗漢
Tsung-Han Tsai
李佩君
Pei-Jun Lee
沈中安
Chung-An Shen
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 74
中文關鍵詞: 卷積神經網路卷積神經網路加速器布氏乘法器資料複用資料流
外文關鍵詞: convolutional neural networks, CNN accelerators, booth multiplier, reused data flow
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  • 近年來,卷積神經網絡由於在提取複雜特徵上有著突出的表現,而被應用於許多領域。然而這些神經網路模型雖然強大但是伴隨著大量運算複雜度。因此有大量研究探討各種神經網路加速器架構和資料流以提升吞吐量和優化能源效率。本文提出了一種混合複用資料流和一種改良版的布氏乘法器以降低能源消耗。評估方式使用批次大小為3的預訓練VGG16模型當作標準。評估結果表明,與先前研究先比,提出的布氏乘法器中的狀態切換次數減少了1.96倍,並且將動態隨機存取記憶體(DRAM)和資料緩衝器存取資料量分別減少至先前研究的92.6%和69.6%。


    In recent years, the convolutional neural networks (CNNs) have been applied to many fields due to its high performance for extracting complex features. However, these CNNs models are robust but come at the cost of lots of computational complexity. As a result, a bunch of studies researches the various architecture and data flow for optimizing the throughput and energy-efficient. This thesis presents a hybrid reused data flow and a modified booth multiplier to reduce energy consumption. The evaluation result uses the pre-trained VGG16 model with a batch size of three as a benchmark. The result shows that the proposed design reduces the number of state toggles in the booth multiplier by 1.96 times and reduces the DRAM and global buffer accesses to 92.6% and 69.6% as prior work respectively.

    Recommendation Form I Committee Form II Chinese abstract III English abstract IV Acknowledgments V Table of Contents VII List of Tables IX List of Figures X Chapter 1 Introduction 1 1.1. Introduction of convolutional accelerator 1 1.2. Challenges of existing works 3 1.3. Contributions of this thesis 4 1.4. Organization 6 Chapter 2 Background 7 2.1. The CNN algorithm 7 2.2. The booth multiplier 17 Chapter 3 Related works 22 3.1. Quantization neural network 22 3.2. CNN accelerators 24 3.3. Optimized MAC units 25 Chapter 4 Proposed data flow and analysis 27 4.1. The hybrid reused data flow 27 4.2. Data analysis of the input operands 32 Chapter 5 Proposed architecture 37 5.1. Top-level architecture 37 5.2. Architecture of the PE 39 5.3. The shift and difference-add booth multiplier 39 Chapter 6 Evaluation 45 6.1. Implementation setup 45 6.2. The memory accesses 46 6.3. The state toggle of the accumulation register 48 6.4. Resource utilization comparison 50 6.5. Throughput comparison 51 Chapter 7 Conclusion 53 Reference 54

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