本篇論文設計一應用於聲頻之離散時間混和強健式MASH-21三角積分調變器。系統藉由消除第一級量化雜訊以提升相較於SMASH-21架構約3 dB的訊雜比，並且有三至四階的雜訊移頻效果。本系統使用全差動架構的電路實現，以抑制偶次項諧波在電路中的影響，進一步提升系統的線性度以及解析度。由於本系統為離散時間系統，因此使用反相與非反相切換式電容積分器來實現離散時間積分器。
本篇論文所設計之晶片使用TSMC 0.18-μm CMOS 製程，操作電壓為1 V， 晶片總功率消耗807.5 μW，總面積為3.096 mm2。系統頻寬22.05 kHz，取樣頻率4.2336 MHz，超取樣率為96倍。晶片解析度(SNDR)可達76.22 dB，等效位元12.37位元。

This paper presents a discrete-time hybrid sturdy MASH-21 (HSMASH-21) delta-sigma modulator for audio applications. The system is able to cancel first stage quantization noise mathematically, which provides a 3-dB signal-to-noise ratio (SNR) improvement over a SMASH-21 system. This work employs fully differential operational transconductance amplifier (OTA) to reduce the impact of even-mode harmonics. Inverting and non-inverting switched-capacitor integrators are used for realizing discrete-time integrators.
The proposed circuit is designed and realized in TSMC 0.18-μm CMOS technology. The supply voltage is 1 V and the chip consumes 807.5 μW of power. The sampling rate is 4.2336 MHz and the oversampling ratio is 96. The achieved signal-to-noise-and-distortion-ratio (SNDR) of the chip is 76.22 dB. The chip occupies an area of 3.096 mm2.

[1] Richard Schreier, Gabor C. Temes, Understanding Delta-Sigma Data Converters. NY: Wiley- Interscience, 2005.
[2] Jose M. de la Rosa, “Design Considerations of ΣΔM Subcircuits,” in Sigma-Delta Converters: Practical Design Guide, IEEE, 2018, pp.301-340.
[3] C.-Y. Yao, “Analysis of a New Hybrid Sturdy MASH-11 Delta-Sigma Modulator,” IEEE 2019 4th International Conference on Intelligent Green Building and Smart Grid (IGBSG), Hubei, Yi-chang, China, Sept. 2019, pp. 362-365.
[4] B. Razavi, Design of Analog CMOS Integrated Circuit. US, McGraw-Hill, 2001.
[5] 張庭卉，「音訊應用等效11.75位元之改良強健式MASH-21三角積分類比數位轉換器」，國立台灣科技大學電機工程系碩士論文，中華民國一百零八年四月。
[6] G. A. S. Machado, N. C. Battersby, and C. Tomazou, “On the Development of Analogue Sampled-Data Signal Processing,” in Proc. Analog Integrated Circuits and Signal Processing, vol. 12, no. 3, Apr. 1997, pp. 179-199.
[7] N. Maghari, S. Kwon and U. Moon, “74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain,” in IEEE Journal of Solid-State Circuits, vol. 44, no. 8, pp. 2212-2221, Aug. 2009.
[8] Y.-H. Liu, C.-Y. Yao, and T.-H. Chang, “A Low-Power 11.1-bit Modified Sturdy MASH-21 Δ-Σ Modulator,” VLSICAD, Aug. 2018.
[9] Libin Yao, M. S. J. Steyaert and W. Sansen, “A 1-V 140 μW 88-dB audio sigma-delta modulator in 90-nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 39, no. 11, pp. 1809-1818, Nov. 2004.
[10] S. Liao and J. Wu, “A 1-V 175-μW 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques,” in IEEE Journal of Solid-State Circuits, vol. 54, no. 9, pp. 2523-2531, Sept. 2019.
[11] T. Chang and C. Yao, “A 11.75-bit Hybrid Sturdy MASH-21 Δ-Σ Modulator for Audio Applications,” 2019 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), Taipei, Taiwan, 2019, pp. 1-2.