交通號誌燈控制是裁決交通路口路權的使用，以一般十字路口為例，除了要決定由那一方向的車流使用路權之外，還要決定其持續佔用的時間。傳統號誌燈控制的方法主要是以固定時間來輪替路權的使用，其缺點是無法反應實際不同向車流的需求，致使路口使用率以及行車等待時間無法有效掌握。將路權分派塑模為資源爭奪的問題，本論文提出以權衡性邏輯為基礎的號誌燈控制方法，它能在考量燈誌切換的上下限的限制，按各奪路權車道上當時的車流量決定路權的分派，以及分派後持續佔用路權的時間。利用權衡分析圖分定系統出衝突的情況下裁決的法則，其最後的控制決策可利用附帶變數之有限狀態機模型 (FSMD) 來表示，並可當作後續直接在像FPGA等內嵌式控制平台上實現的依據。本論文就單一十字路口，以及臨近平交道旁十字路口的號誌燈控制進行分析與設計。除了搭配由Java撰寫的軟體當作模擬, 驗證出本論文所提方案優於固定時間式的交通號誌控制法則外，由權衡式邏輯所推導的號誌燈控制法則並以Verilog HDL實現在FPGA上。本論文所提以權衡式邏輯為依據的資源分派決策法則亦可推廣至一般涉及多方爭奪的資源分配問題。

Traffic signal control at traffic intersections refers to the decision of the access right to a particular lane such that no collision will occur, as well as the allocation time, which affects system utilization. Conventional approaches are dominated by fixed-time switching policy, which, albeit simple, may not yield maximal intersection utilization nor minimal waiting time for the cars queued at the intersection in that real-time traffic is not considered. Formulating the decision problem as a resource contention one, this paper proposes a traffic signal control policy which is based on a defeasible logic scheme: Traffic flows at competing lanes are compared as defeasible rules with the access right granted to the one with heavier traffic; meanwhile, definite rules such as constraint on switching time of signals are also taken into account. With the aid of defeasible graph, conflicts among competing parties are identified and arbitraged accordingly, which leads to a FMSD modeling of the final control decision. Two cases are studied thoroughly: a single intersection, and an intersection in the vicinity of a railway crossroad. Software simulation coded in Java shows that the proposed approach yields better performance over a fixed-time approach. Controllers that embed the defeasible logic rules are also implemented by Verilog HDL on a FPGA to show its ready implementation. The defeasible logic based control proposed in this paper can be also extended to general resource allocation problems when real-time information regarding competing parties are available for defeasible reasoning.

[1] http://traffic.tccg.gov.tw/yearly/almanac01-3.asp?index=5
[2] http://traffic.tycg.gov.tw/plan/planB/upt.asp?cid=1&p0=69
[3] 張智華，張堂賢，<應用智慧型號誌控制器執行適應性控制之研究>，國立臺灣大學土木工程學研究所(2002)
[4] 張明惠，<四種現代化適應性號誌控制邏輯（OPAC、MOVA、SAST、COMDYCS-Ⅲ）之比較研究>，成功大學交研所(1993)
[5] 黃泰林，<構建智慧型適應性網路號誌控制模式之研究>，成功大學交研所
[6] Lin, F.B., “A Comparative Analysis of Two Logics for Adaptive Control of Isolated Intersections”, presented at the 67th Annual Meeting of transportation Research Board, Washington, D.C., and January 11-14, 1988.
[7] Gartner, N.H., “A Prescription for Demand-Responsive Urban Traffic Control”, Transportation Research Record 881, TRB, pp.73-76, 1982.
[8] Gartner, N.H., “OPAC:A Demand-Responsive Strategy for Traffic Signal Control”, Transportation Research Record 906, TRB, pp.75-81, 1983.
[9] Vincent, R.A., and Young, J.R., “Self-Optimising Traffic Signal Control Using Microprocessors – The TRRL MOVA Strategy for Isolated Intersections”, Traffic Engineering and Control, Vol. 27, No. 7, pp. 385-387, 1986.
[10] 邱素文，<最適化控制理論應用於構建獨立路口適應性號誌時制決策邏輯之分析研究>，成功大學交研所(1992)
[11] Hong K. Lo, Y.C. Chan, Andy H.F. Chow, “A New Dynamic Traffic Control System: Performance of Adaptive Control Strategies for Over-saturated Traffic”, 2001.
[12] Pitu Mirchandani, and Larry Head, “A real-time traffic signal control system：architecture, algorithms, and analysis”, Transportation Research Part C 9, pp.415-432,2001.
[13] http://www.moi.gov.tw/stat/
[14] http://www.motc.gov.tw/hypage.cgi?HYPAGE=stat01.asp
[15] Yi, Jiang, Shuo Li, and Daniel E. Shamo, “A platoon-based traffic signal timing algorithm for major-minor intersection types,” Transportation Research Part B, Received 24 April 2003； received in revised form 17 September 2004； accepted 18 July 2005
[16] K. Nakamatsu, T. Seno, J. M. Abe, and A. Suzuki, “Intelligent Real-time Traffic Signal Control Based on a Paraconsistent Logic Program EVALPSN,” Rough Sets, Fuzzy Sets, Data Mining, and Granular Computing: 9th International Conference, vol.2693/2003, pp.719-723, 26-29 May 2003.
[17] S. Sen and L. Head, “controlled optimization of phases at an intersection,” Transp. Sci., vol. 31, pp.5-17, 1997.
[18] P.B. Hunt, D.L. Robertson, and R.D. Bretherton, “The SCOOT on-line traffic signal optimization technique,” Traffic Eng. Control, vol. 23, pp. 190-192, 1982.
[19] Michael A. Covington, “Logical Control of an Elevator with Defeasible Logic,” IEEE Transactions on Automatic control, vol. 45, no. 7, pp. 1347-1349, July 2000.
[20] G. Antoniou, A. Bikakis, and G. Wagner, “A Defeasible Logic Programming System for the Web,” Proceedings of the 16th IEEE International Conference on Tools with Artificial Intelligence(ICTAI 2004)
[21] http://citeseer.ist.psu.edu/correct/36589
[22] http://en.wikipedia.org/wiki/Defeasible reasoning
[23] G. Antoniou, D. Billington, G. Governatori, and M.J. Macher. “Representation Results for Defeasible Logic,” ACM Transactions on Computational Logic, Vol. 2, No.2, pp. 255-287. April 2001.
[24] D. Nute and K. Erk, “Defeasible logic graphs for decision support,” Proceedings of the Twenty-Ninth Hawaii International Conference, Vol. 2, pp. 11-19. 3-6 Jan. 1996.
[25] F. Vahid and T. Givargis, <Embedded System Design>, John Wiley & Sons, Inc., 2002.
[26] C. G.. Cassandras and S. Lafortune, <Introduction to Discrete Event Systems>, Kluwer Academic Publicshers, 1999.
[27] Y. Kim, S. Kopuri, and N. Mansouri, “Automated Formal Verification of Scheduling Process using Finite State Machines with Datapath(FSMD),” Quality Electronic Design, 2004. Proceedings. 5th International Symposium on 2004 pp.110 – 115.
[28] D. D. Gajski, “Introduction to High-Level Synthesis,” IEEE Design & Test of Computers, pp. 44-54. Winter 1994.
[29] Ming-Bo Lin, <FPGA Systems Design and Practice>, Fall 2005.
[30] 林右文，陳慶順，呂嘉弘，”以FPGA實現交通號誌控制器”, 2004中華民國自動控制研討會, 大葉大學, 93年3月
[31] http://www.willbo.com/p6.html#12-1