複晶矽薄膜電晶體(Poly-Si TFTs)已經廣泛被應用在不同的產品上，例如：靜態隨機處理記憶體(SRAMs)、光偵測放大器、掃描器、主動式矩陣液晶顯示器(AMLCDs)等，原因在於複晶矽薄膜電晶體比非晶矽薄膜電晶體具有較高的電子移動率(field effect mobility)，進而增進了同時將主動矩陣及周邊驅動電路整合在同一基板上的能力。然而，傳統的自我對準(self-aligned)複晶矽薄膜電晶體在電特性上卻存在了幾個不欲發生的效應，包括大的關閉狀態(off-state)的電流(leakage current，漏電流)，紐結效應(kink effect)和熱載子效應引起電性操作上的不穩定性。這些效應主要是由於在汲極旁邊的高側向電場所引起。因此，必須降低該電場以改善上述的現象。為了改善元件特性及簡化製程，本論文將分析擁有大角度離子佈植透過間隙壁(Large-angle-tilt-implantation-through-spacer, LATITS)與異質結構複晶矽鍺 (silicon germanium)/矽之薄膜電晶體。
首先，製造三種擁有不同汲極結構的複晶矽薄膜電晶體，分別是：傳統型單一汲極/源極的薄膜電晶體、擁有輕摻雜汲極(LDD)結構的薄膜電晶體以及擁有大角度離子佈植透過間隙壁(LATITS)結構的薄膜電晶體。接著，我們研究用不同的製程參數所形成的LATITS 薄膜電晶體的電特性，例如LATITS的佈植劑量、佈植能量及佈植角度。接下來，我們比較傳統型單一汲極/源極的薄膜電晶體、擁有輕摻雜汲極(LDD)結構的薄膜電晶體以及擁有大角度離子佈植透過間隙壁(LATITS)結構的薄膜電晶體的電特性。結果顯示擁有大角度離子佈植透過間隙壁(LATITS)結構的薄膜電晶體比起傳統型單一汲極/源極的薄膜電晶體、擁有輕摻雜汲極(LDD)結構的薄膜電晶體將會擁有更低的漏電流。因為它對藉由陷阱狀態所產生的載子發射機制能更有效的抑制。因此，擁有大角度離子佈植透過間隙壁(LATITS)結構的薄膜電晶體將可以達到優越的元件特性以及可靠度。
最後，我們探討異質結構複晶矽鍺 (silicon germanium)/複晶矽的薄膜電晶體。藉由改變不同複晶矽鍺與複晶矽的薄膜厚度，研究薄膜厚度對不同汲極電壓的影響，結果發現在低汲極電壓時，較薄的薄膜對抑制貫穿(punch-through)能力較好且起始電壓(threshold voltage)也較低。此外，由於複晶矽鍺的能階(band gap)比複晶矽小，所以複晶矽鍺薄膜電晶體比複晶矽薄膜電晶體的導通電流還要大。相反的，複晶矽薄膜電晶體的漏電流卻是比複晶矽鍺薄膜電晶體還低。而我們可以利用異質結構的方式得到高導通電流且低漏電流的特性。接著改變不同複晶矽鍺和複晶矽的厚度，研究兩種材料對元件特性的影響。而調整閘極氧化層厚度可以發現，當閘極氧化層厚度減少時，因為閘極的控制能力變好，所以導通電流與漏電流皆有明顯增加。

Polycrystalline silicon thin-film-transistors (Poly-Si TFTs) have been widely used in various applications, such as static random memories (SRAMs), photodetector amplifier, scanner, and active matrix liquid crystal displays (AMLCDs). The electron field mobility of the ploy-Si TFT is larger than that of the amorphous-Si (a-Si) TFT, allowing the integration of both active matrix and driving circuitry on the same substrate. However, the conventional self-aligned poly-si TFT induces several undesired effects in the electrical characteristics, including large off-state currents (leakage), kink effect and hot carrier instabilities. These effects are related to the presence of high electric fields at the drain junction and electric field near the drain region relief is essential. In order to improve the electrical properties of devices and process simplification, in this thesis, poly-Si TFTs formed by using the large-angle-tilt-implantation-through-spacer (LATITS) scheme and the hetero-structure poly-SiGe/poly-Si TFT scheme have been analyzed.
First, three types TFTs with different drain structures were fabricated. They are the conventional single source/drain TFT, the Lightly-Doped-Drain (LDD) TFT and the large-angle-tilt-implantation-through-spacer (LATITS) TFT. Next, the electrical characteristics of LATITS TFTs formed with different fabrication parameters such as implantation dose, implantation energy and implantation tilt angle were investigated. And then, the electrical characteristics of the conventional single source/drain TFT, the LDD TFT, and the LATITS TFT were compared. It could be found that the LATITS TFT causes much smaller leakage current than both the conventional single source/drain TFT and the LDD TFT, attributable to the more effective suppression of carrier emission via trap states. As a result, a poly-Si TFT with excellent device characteristics and reliability can be implemented by simply using the LATITS fabrication scheme.
Finally, the hetero-structure poly-SiGe/poly-Si TFT was studied. By changing the thickness of poly-SiGe and ploy-Si as well as studying the influence of different drain voltages. At low drain bias, it’s found that a thinner channel layer has the better ability to suppress the bulk punch-through, and the threshold voltage is lower. In addition, because the band gap of the poly-SiGe TFT is smaller than that of the poly-Si TFT, thus the poly-SiGe TFT shows a larger driving current. However, the leakage current for the poly-Si TFT is lower than that for the poly-SiGe TFT. Hence, we can use the hetero-structure poly-SiGe/poly-Si TFT to get a higher driving current and a lower leakage current. On the other hand, the channel layer thickness of the poly-SiGe TFT and the poly-Si TFT is changed to study its influence on device characteristics. The on-current and the leakage current are obviously increased when the gate oxide thickness is decreased, due to the better gate control ability.

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