隨著CMOS製程技術的進步，SOC的複雜度越來越高，操作時脈較以往增加許多，因此如何讓系統達到時脈同步是一個重要議題。本論文針對目前文獻上有關全數位延遲鎖定迴路的不足處提出一種新的演算法，設計結果節省許多控制電路，在操作頻率60 MHz到1.2 GHz皆能固定在33 cycles後鎖定。目前文獻上的延遲鎖定迴路大多是不固定的鎖定週期，且高頻與低頻的搜索週期差距甚大，應用在系統中，需要一個等待鎖定的訊號，而若是固定週期鎖定，系統只需要計數固定週期後就可以直接進入工作模式，在SOC整合上更為方便。另本論文以cell-based流程完成，使系統具備可攜性，可在不同的製程實現，比較本論文以cell-base流程設計的延遲線及以full-custom流程設計之延遲線，前者具有較佳的線性度。本論文之電路以台積電0.18 um CMOS製程設計驗證，面積為0.689 mm × 0.76 mm，功耗在1.2 GHz的頻率時為16.2 mW，RMS jitter的量測結果在1.2 GHz的頻率下，經de-embedding J-BERT的jitter後為1.95 ps。

With the progress of CMOS technologies, the complexity of the system on a chip (SOC) and the SOC’s operating frequency are dramatically increasing. To achieve system synchronization in an SOC in such high clock rate is an important task. Thus, a low-power high-performance delay-locked loop (DLL) is required for clock synchronization in an SOC. This thesis proposes a new algorithm for designing an all-digital DLL (ADDLL). It can save many control circuits such that the chip area is smaller than most of the ADDLL chip in the literatures. The lock range of the proposed ADDLL is from 60 MHz to 1.2 GHz. That is, its search capability covers a very wide frequency band. On the other hand, it possesses constant lock cycles. The lock time is always 33 cycles no matter what rate the input clock is. The advantage of a constant-lock-cycle DLL is that there is no need to detect the lock condition of the DLL. The system can enter the normal mode of operation after counting a constant periods of its input. This makes it convenient for the SOC integration.
The main circuits (including the delay line) of the proposed ADDLL are designed using the cell-based designed flow. The delay line of the proposed ADDLL shows better linearity than its full-custom counterpart. The chip is realized in TSMC 0.18 um CMOS technology. The chip area is 0.689 mm × 0.76 mm. The power consumption at 1.2 GHz clock rate is 16.2 mW. After de-embedding the J-BERT’s jitter, the RMS jitter performance of the proposed ADDLL achieves 1.95 ps at 1.2 GHz clock rate.

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