硬體FFT處理器廣泛地應用於通訊系統中，而對於不同的用途，將會使用不同運算點數的FFT處理器，因此若能快速產生符合不同應用的FFT處理器，將有助於縮短系統的開發設計時間。
本論文分析不同運算點數的FFT處理器，找出其運算規律性及模組化的硬體架構，透過C語言實現一個能自動產生8點到8192點範圍內不同運算點數的FFT IP產生器，該產生器可根據使用者給定的輸入參數，自動化產生FFT IP (Verilog code) ，而產生器自動化產生的FFT IP還具備簡單內建自我測試功能，用來提高FFT IP的可靠性。另外，產生器自動化產生的FFT IP，將以北瀚科技驗證平台搭配Altera StratixII EP2S60F1020C5NK FPGA，驗證本論文設計之FFT IP硬體電路的正確性。

FFT processors are widely used in communication systems. In different applications, different size FFT processors are employed. This thesis presents an FFT IP generator such that the designer can obtain an FFT soft IP in a few second.
This thesis first analyzes the advantage of different FFT architectures. Next, an SDF architecture is used for the proposed FFT IP generator because SDF has the simplest hardware architecture. The generator can generate 8-to 8192-point FFT IP with variable input wordlength. A built-in self test circuit is also generated to accompany the FFT IP such that the IP can be easily tested. The generated 8-to 8192-point FFT IPs are all verified on the Altera StratixⅡ FPGA board.

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