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研究生： 鄭子凡
Tsi-fan Cheng
論文名稱： 以多組CMOS感測器實現高速攝影系統之SOPC硬體架構
Implementing the SOPC Hardware Structure of the High Speed Camera via Multiple CMOS Sensors
指導教授： 許孟超
Mon-chau Shie
口試委員: 阮聖彰
none
鄭瑞光
none
粱文耀
none
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2007
畢業學年度： 95
語文別： 中文
論文頁數： 56
中文關鍵詞： 視覺暫留 、高速攝影機 、CMOS Camera 、JPEG 、SOPC 、FPGA
外文關鍵詞： Photogene, High-Speed, CMOS Camera, JPEG, SOPC, FPGA
相關次數： 點閱：177  下載：3 
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    • 由於人眼有視覺暫留的現象，影像會在視網膜上殘留約0.1秒才消失，所以無法分辨太高速的影像變化，因此在許多工程或是學術研究環境中，例如車輛撞擊測試，火箭發射及自動化生產線測試等，高速攝影機的應用都非常廣泛，它能夠以每秒至少500張畫面以上的攝影速度拍攝，讓人觀察到事件發生的瞬間，也由於高速攝影機比一般攝影機的能力高出許多，所以價格非常昂貴。
    本論文利用在一般消費性電子產品中使用廣泛的CMOS Camera，以同時連接多組的方式形成高速攝影系統，並設計硬體JPEG壓縮模組對被攝影之影像進行即時壓縮，以降低頻寬以及記憶體容量需求，最後再借由具有高整合度的SOPC技術，將系統實現於單顆FPGA晶片中，本論文提出的架構能夠很容易增減系統連接的CMOS Camera數量，且成本將比一般高速攝影機更低。

    Due to the photogene of the human eyes, there is about 0.1 second persistence in the retina. So high-speed variations of images are difficulty recognized. Therefore, around the engineering science researches, such as the impaction experience of mobile, rocket launch and automatic production, the high-speed camera is applied widely. For observing the moment where an event happens, the high-speed cameras provide a picturing ability which is taken five hundred frames per second at least. Thus, the high-speed camera is much more expensive than the general one.
    In this paper, we use CMOS cameras widely used in electric consumer products. A high-speed picturing system is consisted of many CMOS cameras. JPEG compression hardware module is designed to compress videos captured by the high-speed picturing system in real time and reduce requirements for the bandwidth and memory. Finally, the system is implemented in a FPGA chip by the high-integrated SOPC technology. The architecture proposed in this paper can increase or reduce the number of CMOS cameras easily, and the cost of which is much fewer than the general high-speed camera.

    論文摘要............................................................1 Abstract............................................................2 致謝................................................................3 目錄................................................................4 圖索引..............................................................6 表索引..............................................................8 第一章 序論...............................................9 1.1 研究動機與目的..............................................9 1.2 研究背景....................................................9 1.3 全文架構...................................................10 第二章 相關知識..........................................11 2.1 攝影原理...................................................11 2.2 CMOS Camera................................................12 2.3 JPEG影像壓縮...............................................15 2.3.1 色相轉換.............................................16 2.3.2 離散餘弦轉換.........................................16 2.3.3 量化.................................................18 2.3.4 Zig-Zag掃描..........................................19 2.3.5 熵編碼...............................................20 2.4 SOPC技術與Avalon Bus......................................23 2.4.1 NIOS II..............................................24 2.4.2 Avalon Bus...........................................25 第三章 Multiple CMOS Camera高速攝影系統...................27 3.1 系統特性...................................................27 3.2 系統架構...................................................28 3.3 Multiple CMOS Camera 延遲同步控制電路......................31 3.4 JPEG影像壓縮模組...........................................32 3.4.1 2D-DCT硬體架構.......................................34 3.4.2 量化硬體架構.........................................35 3.4.3 Zig-Zag硬體架構......................................37 3.4.4 熵編碼模組...........................................38 3.4.5 資料儲存.............................................37 3.5 影像輸入...................................................39 3.6 影像輸出...................................................40 3.7 GPU........................................................41 3.8 系統建立與整合.............................................42 第四章 成果與討論........................................45 第五章 結論與未來展望....................................55 參考文獻...........................................................56

    [1] “Information Technology–Digital Compression and Coding of Continuous-tone Still Image-Requirements and Guidelines”, ITU-T Recommendation T.81, 1992. ISO/IEC 10918-1:1993 International Telecommunications Union. (Commonly referred to as JPEG standard)
    [2] 施尚融，高速攝影系統介紹與應用，http://www.artc.org.tw/，財團法人車輛研究測試中心， 2006
    [3] 陳同孝、張真誠、黃國峰，數位影像處理技術，旗標出版社，2003
    [4] 張思恩編譯，Eli Sternhim, Rajvir Singh, Rajeev Madhavan, Yatin Trivedi原著，精通Verilog，台北圖書
    [5] “DE2 Development and Education Board User Manual”, Version 1.0,友晶科技，2005
    [6] “MT9M011 1/3-Inch Megapixel CMOS Active-Pixel Digital Image Sensor Data Sheet”, Micron Technology Inc. 2004
    [7] http://www.altera.com/literature/lit-index.html，Altera官方網頁，2007
    [8] “NIOS II Processor Handbook”, Version 7.1, Altera, 2007
    [9] “Quartus II Handbook Volume 4:SOPC Builder”, Version 7.1, Altera, 2007
    [10] “Cyclone II Device Handbook”, Version 3.1, Altera, 2007

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