以現場可程式化閘陣列實現延遲回繞法為基礎之時間至數位轉換器

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研究生：	賴威諭 Wei-yu Lai
論文名稱：	以現場可程式化閘陣列實現延遲回繞法為基礎之時間至數位轉換器 A Field Programmable Gate Array Time-to-Digital Converter Based On The Wrapping Of Delay
指導教授：	陳伯奇 Poki-Chen
口試委員:	陳建中 Jiann-Jong Chen 黃育賢 Yuh-Shyan Hwang 羅有綱 Yu-Kang Lo
學位類別：	碩士 Master
系所名稱：	電資學院 - 電子工程系 Department of Electronic and Computer Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	中文
論文頁數：	83
中文關鍵詞：	PVT變異抗性、時間至數位轉換電路、延遲回繞、場可程式規劃之邏輯閘陣列
外文關鍵詞：	PVT insensitive, time-to-digital converter, wrapping of delayed, Field programmable gate array (FPGA)
相關次數：	點閱：453 下載：0
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本論文提出一個實現於現場可程式化閘陣列(field programmable gate array, FPGA)並利用延遲回繞法為基礎的時間至數位轉換電路(Time-to-digital converter, TDC)。本論文之TDC不但可以抵抗PVT變異，並且可以達到極高解析度與寬的量測時間範圍。利用FPGA內建之延遲元件，將參考時脈經逐級延遲，再利用週期性參考時脈之延遲回繞(Wrapping)效果，搭配大數法則將計數結果加總平均，以大幅推高解析度，其解析度可高達9.8ps，一樣不隨PVT變異而改變，另外加入了偏移校準技術更進一步的抵抗PVT變異對偏移量的影響。經過長線量測之後量測出本論文之TDC的積分非線性誤差(INL)為-1.96~1.78 LSB；差分非線性誤差(DNL)為-1.75~1.77LSB。並完整測試涵蓋10℃到50℃的運作功能驗證本TDC對抗溫度變異之效果。

A time-to-digital converter (TDC) implemented on field programmable gate array (FPGA) base on the wrapping of delayed is presented. The proposed TDC is aimed to provide a PVT-insensitive TDC solution with high resolution and wide measurement range. The reference clock will be delayed by FPGA delay elements. Since all delayed clocks are still periodic and their relative phases will be wrapped back when the corresponding delays cross over the period boundaries, The test input will be measured by counters triggered by delayed clocks correspondingly and the output will be averaged to get the final TDC output. According to the law of large numbers (LLN), an extremely fine resolution can be expected as long as the number of delayed clocks is large enough. The resolution will be 9.8ps which is also PVT-invariant.The proposed TDC successfully eliminates the offset adjustment with a simple offset cancelation technique. The long-term measurement integral nonlinearity (INL) of this TDC is -1.96~1.78 LSB, and the differential nonlinearity (INL) is -1.75~1.77LSB. This TDC was tested to be fully functional over 10℃ to 50℃ ambient temperature range with extremely low resolution variations.

第一章  序論…………………………………………………………………………………………………………………1
1-1  研究背景…………………………………………………………………………………………………………1
1-2  研究動機…………………………………………………………………………………………………………2
1-3  章節介紹…….…………………………………………………………………………………………………3
第二章  時間至數位轉換電路……………………………………………………………………………………4
2-1  時間至數位轉換電路簡介……………………………………………………………………………4
2-2  時間至數位轉換電路之架構介紹與說明………………………………………………………7
2-2.1  計數器法之時間至數位轉換電路………………………………………………………7
2-2.2  抽頭延遲線式之時間至數位轉換電路………………………………………………12
2-2.3  延遲矩陣式時間至數位轉換電路………………………………………………………15
2-2.4  鏈結構延遲線之時間至數位轉換電路………………………………………………18
2-2.5  數位校準……………………………………………………………………………………………21
2-2.6  以鎖相迴路為基礎之時間至數位轉換電路………………………………………24
2-2.7  結論……………………………………………………………………………………………………27
第三章  以延遲回繞法實現之時間至數位轉換電路………………….………………………………28
3-1  FPGA晶片與本論文所使用的FPGA開發板簡介………………….………………………28
3-2  以延遲回繞法實現之時間至數位轉換電路………………………………………………30
3-2.1  延遲回繞法之概念………………………….………………………………………………31
3-2.2  延遲級部份(Tapped Delay Line)選擇………………………………………………34
3-2.3  計數器陣列(Counter array)……………...………………………………………………38
3-2.3.1  非同步之漣波計數器(Ripple Counter)…………………………………39
3-2.3.2  同步計數器(Synchronous Counter)………………………………………43
3-2.3.3  結論………………………………………………………………………………………45
3-2.4  加總平均電路(Averager)……………….…………………………………………………46
3-2.4.1  以組合邏輯加法器方式…………………………………………………………46
3-2.4.2  以多工累加器方式………….……………….……………………………………47
3-2.4.3  四捨五入法…………..………………………….……………………………………50
3-2.4.4  結論……………………..………………………….……………………….……………51
3-2.5  自我偏移消除電路(Self Offset Cancelation Circuit)………….…………………52
第四章  FPGA之時脈網路…………………………..………………………………………………………………57
4-1  時脈偏移問題與時脈樹……………………………………..……………………………………57
4-2  Altera Stratix IV系列的時脈網路(Clock Network)………………………………………59
4-3 時脈網路對本論文架構之影響……………………………..………………………………………60
第五章  實驗量測結果與未來展望……………………………………………………………………………61
5-1  量測儀器簡介………………………………………………………………………………………………61
5-2  量測環境的建立……………………………………………………………………………………………65
5-3  量測結果………………………………………………………………………………………………………67
5-3.1  短線測量(Short-Term Measurement)…………………………………………………67
5-3.2  長線測量(Long-Term Measurement)…………………………………………………69
5-3.3  單擊精密度(Single-Shot Precision)測量……………………………………………71
5-3.4  溫度變異測量(Temperature Variation)………………………………………………72
5-3.5  失效時間量測…………………………………….……………………………………………76
5-4  結論與未來展望……………………………………………………………………………………………79
參考文獻………………………………………………………………………………………………………………………80






圖目錄
圖2-1應用於雷射測距儀之時間至數位轉換電路……………………………………………4
圖2-2計數器法之時間至數位轉換電路時序圖………………………………………………………7
圖2-3計數器法之時間至數位轉換電路之誤差………………………………………………………8
圖2-4時間內插器之時序圖…………………………………………………………………………………9
圖2-5時間內插器應用於時間至數位轉換電路的架構圖……………………………………10
圖2-6 以兩條中間抽頭式延遲線之架構圖…………………………………………………………………12
圖2-7 以兩條中間抽頭式延遲線之時序圖…………………………………………………………………13
圖2-8延遲矩陣式時間至數位轉換電路……………………………..……………………………………15
圖 2-9  (a)延遲級內部電路 (b)上升緣到脈衝產生電路..……………………….……………….…16
圖2-10進位鏈結構之時間至數位轉換電路的架構圖…………………………………………………18
圖2-11進位鏈結構之實現電路示意圖……………………………………………………..…………………19
圖2-12數位校準電路……………………………………………………………………………………………………22
圖2-13統計逼近(Statistical Approach)校準電路之示意圖……………………………………………23
圖2-14傳統多相位時間至數位轉換電路簡化後架構圖……………………………..………………24
圖2-15 (a) 多重相位之時間至數位轉換電路使用四個相位實現 (b) 多重相位之時間至數位轉換電路使用八個相位實現且提高時脈頻率…….……………………………………………25
圖2-16多重計數器之時間至數位轉換電路細調時間至數位轉換電路之架構圖……….26
圖3-1以延遲回繞法實現之時間至數位轉換電路原始架構圖……………………….……………30
圖3-2參考時脈延遲線之理想時序圖……………………………………………………………………..……31
圖3-3延遲回繞效應與有效幾析度之關係圖………………………………………….……………………32
圖3-4進位鏈取代延遲級………………………………………………………………………………………………34
圖3-5 (a)內建於FPGA內之進位鏈LUT  (b)進位鏈延遲圖 (c)跨LUT延遲圖……..………35
圖3-6時脈縮減及消失圖………………………………………………………………………………………………35
圖3-7以Inverter取代非反向Buffer………………………………………………………………………………36
圖3-8以延遲回繞法實現之時間至數位轉換電路修改後架構圖…………………………………37
圖3-9計數器陣列的細部電路圖………………………………..…………………………………………………38
圖3-10非同步之漣波計數器合成圖…………………….………………………………………………………39
圖3-11漣波計數器之模擬圖………………..………………………………………………………………………40
圖3-12漣波計數器的最長路徑.……………………………………………………………………………………40
圖3-13漣波計數器的非理想特性…………………………………………………………………………………41
圖3-14漣波計數器的後模擬圖(時脈週期為10ns)……………………………….………………………42
圖3-15漣波計數器的後模擬圖(時脈週期為5ns)…………………………………………………………42
圖3-16同步計數器電路合成圖………………………………………………….…………………………………43
圖3-17同步計數器之模擬圖…………………………………………………………………………………………44
圖3-18同步計數器之最長路徑…………………….………………………………………………………………44
圖3-19串相加之加法器合成圖………………………….…………………………………………………………46
圖3-20分組相加之加法器合成圖…………………………………………………………………………………47
圖3-21累加器之時序圖…………………………………………………………..……………………………………47
圖3-22多工累加器之電路圖…………………………………………………………………………………………48
圖3-23組合邏輯電路搭配多工累加器示意圖……………………………………..………………………49
圖3-24使用LUT數與運算時間關係圖………………………………………………………….………………49
圖3-25二進制之四捨五入法……………………………………………………………................……………50
圖3-26溫度對偏移量示意圖…………………………………………………………………………………………52
圖3-27典型之時間至數位轉換電路輸出曲線…………..…………………………………………………53
圖3-28自我偏移消除電路架構圖…………………………………………………………………………………54
圖3-29量測狀態時資料傳遞路徑…………………………………………………………………………………54
圖3-30 1T累加狀態時資料傳遞路徑………………………………………………….…………………………55
圖3-31 2T累減狀態時資料傳遞路徑………………………………………………….…………………………55
圖4-1 8x8的網路作為H型時脈樹……………………………………………………………..…………………58
圖4-2 (a)全域時脈之簡單示意圖 (b)區域時脈之簡單示意圖…………….………………………59
圖5-1 Altera Sratix IV EP4SGX230KF40C2ES………………………..………………………………………61
圖5-2 Agilent 81134A儀器實體照片…………………….....…………………………………………………63
圖5-3 Tektronix DPO70404儀器實體照片…………………………………………………..…………………64
圖5-4 TERCHY T6800儀器實體照片………………………………………………………………………………64
圖5-5本論文之量測環境………………………………………………………………………………………………65
圖5-6 ALTERA Stratix II GX FPGA Development Kit………………………….………………………………66
圖5-7短線量測特性曲線………………………………………………………………………………………………68
圖5-8短線量測之INL……………………………………………………………………….……………………………68
圖5-9為短線量測之DNL………………………….……………………………………………………………………69
圖5-10長線量測之特性曲線…………………………………………………………………………………………70
圖5-11長線量測之INL……………………………………………….…………………………………………………70
圖5-12長線量測之DNL…………………………………………………………………………………………………71
圖5-13輸入單一時間寬度之Histogram…………………………………..……………………………………72
圖5-14溫度與解析度之關係圖…………………………….………………………………………………………73
圖5-15溫度與精密度之關係圖…………….………………………………………………………………………73
圖5-16溫度與偏移量之關係圖…………………….………………………………………………………………74
圖5-17校準前的轉換曲線…………………………….………………………………………………………………74
圖5-18校準後的轉換曲線……………………………………….……………………………………………………75
圖5-19失效時間至量測示意圖……………………….……………….……………………..……………………76







表目錄
表(3-1) ─頻率、級數、標準差、解析度關係表………………………………………………..………50
表(3-2) ─四捨五入後之頻率、級數、標準差、解析度關係表………………………………………51
表(5-1) ─Agilent 81134A之重要規格特性…………………………………………………………………62
表(5-2) ─Tektronix DPO70404之重要規格特性…………………………………………………………61
表(5-3) ─ 本論文電路架構之預期規格……………..………………………………………………………77
表(5-4) ─ 本論文電路架構之規格……………………………..………………………………………………77
表(5-5) ─ 相關文獻比較表………………………………………..………………………………………………78

                                

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