近年來，深度神經網路 (Deep Neural Network, DNN) 被廣泛的應用在許多領域之中，例如自動駕駛、影像辨識以及生物醫學電子設備等，皆可達到一定的正確率 (Accuracy)，而使用傳統馮諾伊曼 (Von Neumann) 計算機架構，在計算神經網路矩陣或是向量的相乘時，往往會耗費許多時間以及功耗在記憶體單元與計算單元之間的資料搬移上，因而無法達成即時 (Real time) 辨識的效果，而使用電阻式記憶體 (Resistive Random Access Memory, RRAM) 可以有效率的解決這個問題，其面積與功率的效率都比使用馮諾伊曼架構高。
然而由於製程尚未成熟，在RRAM細胞陣列中，會有許多的錯誤發生，導致矩陣計算時的誤差，進而影響正確率。為了提升使用RRAM運算時的正確率，以往的技術也提出許多容錯技術 [1, 2, 3]。而本篇論文提出權重 (Weight) 矩陣的位址重映射 (Address Remapping, AR) 及錯誤抵抗訓練 (Fault Resilient Training, FRT) 技術，位址重映射技術嘗試避免正負記憶體矩陣中相同邏輯位址發生錯誤的情況，並且提升使用另一個矩陣修復權重值的機率；錯誤抵抗訓練技術則將權重值訓練成集中在原點分布的情形，以減少錯誤發生時所造成的效應，此兩種技術可省略在 [1, 2] 所提技術中，為了實現將記憶體實體 (Physical) 位址更改成任意邏輯 (Logical) 位址的繞線器，且無須根據錯誤的分布重新訓練神經網路。
本研究中實現了位址重映射器 (Address Remapper) 的電路，並且以pytorch [4] 的深度學習框架模擬了錯誤抵抗訓練技術以及正確率，針對不同的可接受正確率下降 (Acceptable Accuracy Drop, AAD) 定義接受率 (Acceptance Rate, AR)，並取代傳統修復率 (Repair Rate, RR) 的概念，進而以求得的接受率計算良率 (Yield)。依實驗結果可知，在錯誤比率為10% 且可接受正確率下降為5 % 時，使用LeNet5 [5] 推論MNIST [6] 手寫辨識的資料集，錯誤更正技術 [3] 修復後的正確率為87.66%，良率為85.9 %；使用位址重映射技術的正確率可達94.47%，良率為90.7 %；而結合了錯誤抵抗訓練則可將正確率維持為92.85 %，良率為95.5 %；使用的額外硬體成本總和不超過1 %。

Deep Neural Network (DNN) has been widely used in autonomous driving, image recognition and biomedical electronic equipments. However, by using the traditional Von Neumann computer architecture for calculating the massive matrix-vector multiplications usually takes a lot of time and power consumption to move the data between the memory units and the computing units. This make the real-time identification infeasible. To cure this drawback, Resistive Random Access Memory (RRAM) is widely used for in-memory computing. The incurred area and power overhead are less than those using the conventional von Neumann architecture.
However, due to the immature fabrication process of RRAM, many manufacturing defects may exist in the RRAM cell array and result in erroneous matrix-vector multiplication. This will then affect the recognition accuracy for DNN applications. In order to improve the accuracy when using neuromorphic computing based on RRAM, there are many fault-tolerant techniques proposed [1, 2, 3].
This research project proposed the address remapping (AR) and the fault resilient training (FRT) techniques for mitigating the effects of defective RRAM cells. The AR technique tries to avoid defective cells occurring at the same logical addresses in the positive and the negative memory matrices. Therefore, the probability of using another matrix to compensate the weight value of faulty cells can be greatly improved. FRT technique trains the weight value distributions concentrating to the origin such that the effects of faults can be reduced. These two proposed techniques do not require the complex router used in [1, 2] to realize the mapping of a physical address to an arbitrary logical address. Moreover, it is not necessary to retrain the neural network according to the fault distributions.
The architecture of the address remapper for the AR technique is also proposed. We use the deep learning frameworkpytorch [4] for evaluating the accuracy. Moreover, the acceptance rate (AR) is defined based on the specified acceptable accuracy drop (AAD). Instead of the conventional concepts for evaluating repair rate and yield, AAD is used as the measure for estimating the effective repair rate and yield.
When the injected fault percentage is 10% and the AAD is 5%, we use LeNet5 [5] to inference the MNIST [6] handwriting recognition data set. The accuracy and yield after repair are 87.66 % and 85.9 %, respectively by using the error correction technique [3]. For the proposed AR technique, the accuracy and yield can be improved up to 94.47% and 90.07%, respectively. If the FRT and the AR techniques are both equipped, the accuracy and yield can be further enhanced to 95.83% and 95.49%, respectively. The hardware overhead for implementing both techniques is less than 0.4%.

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