我們創造出一種新穎的暫存器架構，結合累加器以及暫存器的優點，可有效提升暫存器數目且不需增加編碼空間，使得編譯器或程式設計師可以使用更多的暫存器來提高程式的效率。

This paper presents a new ISA called floating accumulator architecture (FAA) that can expand the number of ISA registers without increasing the instruction length. Unlike the accumulator architecture whose accumulator is a fixed, special register, FAA dynamically chooses a register from the general-purpose register file as the accumulator. Since the accumulator implicitly stores the result, the destination register field can be omitted from FAA instructions, resulting in a saving of 3 to 5 bits for each instruction.

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