簡易檢索 / 詳目顯示

研究生: 葉修安
Hsiu-An Yeh
論文名稱: 四相位壓控振盪器與使用特殊電感架構的注入鎖定除頻器之研究
Research of Quadrature Voltage-Controlled Oscillator and Injection Locked Frequency Dividers Using Special Inductors
指導教授: 張勝良
Sheng-Lyang Jang
口試委員: 徐敬文
Ching-Wen Hsue
黃進芳
Jhin-Fang Huang
黃忠偉
Jong-Woei Whang
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2010
畢業學年度: 98
語文別: 英文
論文頁數: 125
中文關鍵詞: 壓控振盪器注入鎖定除頻器四相位二極體環耦合雙頻帶主動電感三維電感
外文關鍵詞: voltage-controlled oscillator (VCO), injection locked frequency divider (ILFD), quadrature, diode-ring coupling, dual-band, active inductor, 3-dimensinal (3-D) inductor
相關次數: 點閱:273下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 在無線通訊系統中,頻率合成器是用來做訊號頻率的升降之用。其中,壓控振盪器與除頻器更是頻率合成器電路裡的核心電路之ㄧ。對壓控振盪器而言,必須提供低相位雜訊的輸出,以避免相鄰雜訊訊號經由混波轉換產生干擾。而壓控振盪器的輸出會經由除頻器降頻至與參考訊號相同的等級,與相位頻率偵測器做比較以校正壓控振盪器的輸出,故除頻器需要有高頻操作的能力。由於應用於無線通訊系統中,壓控振盪器與除頻器都必須要有低功耗的特性。

    本論文提出了共一個壓控振盪器與兩個除頻器電路。其中壓控振盪器是使用二極體耦合的四相位輸出振盪器。一個使用主動電感的注入鎖定除頻器。以上電路使用台積電0.18微米CMOS製程來完成。另一個則是一個使用三維電感的雙頻帶注入鎖定除頻器,使用聯電90奈米製程去實現。

    首先,我們提出一個將兩組以n型電晶體為核心、透過二極體耦合形成四相位輸出壓控振盪器的技術。當控制電壓由0到1.2 V變化時,四相位壓控振盪器的低頻帶可由4.50 GHz調到4.72 GHz,而高頻帶則由11.61 GHz到11.84 GHz。而在低頻帶輸出頻率4.5 GHz,所量測到的相位雜訊在1 MHz位移時為-115.54 dBc/Hz。

    其次,我們呈現一個使用可調主動電感的低功耗寬鎖定範圍注入鎖定除頻器,其可調主動電感是以兩組交錯耦合電晶體串聯堆疊而成。藉由直接在橫跨於主動LC共振腔的金氧半場效電晶體的閘極端注入訊號,我們可以得到除二的功能。當供給電壓為1.6 V時,振盪頻率為1.3至0.8 GHz。在注入強度為-3dBm時,其除二模數的操作頻率為1.5至3.8GHz。

    最後,我們討論一個雙頻帶的互補式金氧半LC共振腔注入鎖定除頻器,以一個交錯耦合的n型金氧半振盪器與雙頻帶LC共振腔來完成。在這個電路中我們會使用一個三維的變壓器。當直流的閘-源極電壓為0.7 V時,不需透過調整電壓,振盪頻率可以有兩個頻帶,高頻帶約24.4 GHz。低頻帶約5.5 GHz,事實上它是一個激發出來的頻帶。我們量測到的高 (低) 頻帶鎖定範圍為46.5 (10.4) 至51.4 (11.9) GHz。


    In wireless communication system, frequency synthesizers are used to implement the frequency up/down converting of signal. In a frequency synthesizer, voltage-controlled oscillator (VCO) and divider are the key blocks. For VCOs, low phase-noise output is required to avoid corrupting the mixer-converted signal by close interfering tones. The frequency of output signal of VCO is divided down to the level of reference signal, and is compared with reference signal by a phase frequency detector (PFD) to adjust the output of VCO. Therefore the dividers must have the ability of high frequency operation. Because of wireless application, both of them should operate at low power consumption.

    This thesis proposes one VCO and two frequency dividers. The VCO provides quadrature outputs by diode-coupling technique. One divider is an injection locked frequency divider (ILFD) using active-inductor. The above circuits are fabricated in the TSMC 0.18 μm CMOS process. Another one is a dual-resonance ILFD using 3-dimensinal (3-D) transformer implemented in the UMC 90 nm process.

    Firstly, a diode-ring coupling technique has been used to design a quadrature voltage-controlled oscillator (QVCO), which consists of two n-core VCOs. The oscillating low-band frequency of the QVCO can be tuned from 4.50 GHz to 4.72 GHz, and the oscillating high-band frequency of the QVCO can be tuned from 11.61 GHz to 11.84 GHz while the tuning voltage varies from 0 V to 1.2 V. The phase noise of the high band oscillation frequency 4.5 GHz is -115.54 dBc/Hz at 1 MHz frequency offset.

    Secondly, we present a low power wide-locking range ILFD with tunable active inductor (TAI) which is based on two pairs of cross-coupled transistors stacked in series. The divide-by-2 function is performed by injecting a signal to the gate of direct injection MOSFETs across the active LC resonator. At the supply voltage of 1.6 V, the free-running divider is tunable from 1.3 to 0.8 GHz. At the incident power of -3 dBm the operation range in the divide-by-2 mode is from the incident frequency 1.5 to 3.8 GHz.

    Finally, a dual-band CMOS LC-tank ILFD is proposed. It is realized with a cross-coupled nMOS oscillator with a dual-resonance LC-tank. A 3-D transformer is used in the implemented ILFD. At the dc drain-source voltage of 0.7 V, the free-running ILFD can have two frequency bands without tuning, and the high-band oscillation frequency is 24.4 GHz. The low-band oscillation frequency is 5.5 GHz. The low-frequency band is an excited band. The measured locking range is from 46.5 (10.4) GHz to 51.4 (11.9) GHz for the high- (low-) frequency band.

    中文摘要 Abstract 致謝 Contents List of Figures List of Tables CHAPTER 1 INTRODUCTION 1.1 MOTIVATION 1.2 THESIS ORGANIZATION CHAPTER 2 OVERVIEWS OF OSCILLATORS AND INJECTION LOCKED PHENOMENON 2.1 INTRODUCTION 2.2 BASIC THEORY OF OSCILLATORS 2.2.1 ONE-PORT (NEGATIVE RESISTANCE) VIEW 2.2.2 TWO-PORT (FEEDBACK) VIEW 2.3 CLASSIFICATION OF OSCILLATORS 2.3.1 RESONATORLESS OSCILLATORS I. RING OSCILLATOR II. RELAXATION OSCILLATOR 2.3.2 LC-TANK OSCILLATORS I. COLPITTS AND HARTLEY OSCILLATORS II. NEGATIVE-GM OSCILLATORS 2.4 PARALLEL RLC TANK 2.4.1 RESISTORS 2.4.2 INDUCTOR AND TRANSFORMER I. INDUCTOR II. TRANSFORMER 2.4.3 CAPACITORS AND VARACTORS I. CAPACITORS II. MOSFET VARACTORS 2.5 DESIGN CONCEPTS OF VCOS 2.5.1 VCO CHARACTERISTIC PARAMETERS 2.5.2 PHASE NOISE IN OSCILLATORS 2.5.3 QUALITY FACTOR 2.5.4 Pulling in Oscillators 2.5.5 QUADRATURE VCO DESIGN 2.6 INJECTION LOCKED PHENOMENON 2.6.1 PRINCIPLE OF INJECTION LOCKING 2.6.2 OPERATION RANGE CHAPTER 3 A CMOS Dual-Band Quadrature VCO Using the Diode Coupling Technique 3.1 INTRODUCTION 3.2 CIRCUIT DESIGN 3.3 MEASUREMENT RESULTS 3.4 CONCLUSION CHAPTER 4 Low Power Active-Inductor Injection Locked Frequency Divider 4.1 INTRODUCTION 4.2 CIRCUIT DESIGN 4.3 MEASUREMENT RESULTS 4.4 CONCLUSION CHAPTER 5 Dual-Resonance Injection-locked Frequency Divider with 3-Dimensional Inductor 5.1 INTRODUCTION 5.2 CIRCUIT DESIGN 5.3 MEASUREMENT RESULTS 5.4 CONCLUSION CHAPTER 6 CONCLUSION REFERENCES

    [1] N. M. Nguyen, and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE Journal of Solid-State Circuits, vol. 27, pp. 810-820, May 1992.
    [2] S. Smith, Microelectronic Circuit 4th edition, Oxford University Press 1998.
    [3] J. Roggers, C. Plett, Radio frequency integrated circuit design, Artech House, 2003.
    [4] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
    [5] H. M. Greenhouse, “Design of planar rectangular microelectronic inductors,” IEEE Transactions on Parts, Hybrids, and Packaging, vol. 10, pp. 101-109, Jun 1974.
    [6] J. Craninckx and M. S. J. Steyaert, “A 1.8 GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors,” IEEE J. Solid-State Circuits, vol. 32, no. 5, pp. 736–744, May 1997.
    [7] P. Yue, C. Ryu, JackLau, T. Lee, and S. Wong, “A physical model for planar spiral inductors on silicon,” 1996 International Electron Devices Meeting Technical Digest, pp. 155–158, Dec. 1996.
    [8] J. R. Long, “Monolithic transformers for silicon RF IC design,” IEEE Journal of Solid-State Circuits, vol. 35, pp. 1368-1382, Sept. 2000.
    [9] E. Frlan, S. Meszaros, M. Cuhaci, and J.Wight, “Computer-aided design of square spiral transformers and inductors,” in Proc. IEEE MTT-S, pp. 661-664, June 1989.
    [10] P. Andreani, S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 905-910, June 2000.
    [11] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
    [12] J.J. Rael, and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” IEEE Custom Integrated Circuits Conference, pp. 569–572, 2000.
    [13] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326–336, Mar. 2000.
    [14] D. Leeson, “A simple model of feedback oscillator noise spectrum,” Proceedings of the IEEE, vol. 54, pp. 329–330, Feb. 1966.
    [15] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
    [16] A. Hajimiri and T. H. Lee, “Design Issues in CMOS differential LC Oscillators,” IEEE J. Solid-State Circuits, vol. 34, pp. 717–724, May 1999.
    [17] J. Craninckx, and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by-128/ 129 prescaler in 0.7 μm CMOS,” IEEE J. Solid-State Circuits, vol. 31, pp. 890-897, Jul. 1996.
    [18] Q. Huang, and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, pp. 456-463, Mar. 1996.
    [19] J. Lee, and B. Razavi, “A 40 GHz frequency divider in 0.18μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, pp. 594-601, Apr. 2004.
    [20] H. R. Rategh, and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813-821, Jun. 1999.
    [21] H. D. Wohlmuth, and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), pp. 823-826, Sep. 2002.
    [22] M. Tiebout, “A 480 uW 2 GHz ultra low power dual-modulus prescaler in 0.25 μm standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), vol. 5, pp. 741-744, May 2000.
    [23] H. Wu, and A. Hajimiri, “A 19 GHz 0.5 mW 0.35 μm CMOS frequency divider with shunt-peaking locking-range enhancement,” IEEE ISSCC Dig. Tech. Papers, pp. 412-413, Feb. 2001.
    [24] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection- locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, pp. 47-50, Jun. 2001.
    [25] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An injection locking scheme for precision quadrature generation,” IEEE J. Solid-State Circuits, vol. 37, pp. 845-851, Jul. 2002.
    [26] P. Andreani and X. Wang, “On the phase-noise and phase-error performances of multiphase LC CMOS VCOs,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1883–1893, Nov. 2004.
    [27] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz CMOS LC-oscillator with quadrature outputs,” in IEEE ISSCC Dig. Tech. Papers, Feb. 1996, pp. 392–393.
    [28] H.-R. Kim, C.-Y. Cha, S.-M. Oh, M.-S. Yang, and S.-G. Lee, “A very low-power quadrature VCO with back-gate coupling,” IEEE J. Solid-State Circuits, vol.39, no.6, pp.952–955, June 2004.
    [29] S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi, “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1148–1154, July 2003.
    [30] P. Tortori, D. Guermandi, E. Franchi, and A. Gnudi, “Quadrature VCO based on direct second harmonic locking,” in Proc. ISCAS, May 2004, pp. 169–172.
    [31] A. W. L. Ng and H. C. Luong, “A 1-V 17-GHz 5-mW CMOS quadrature VCO based on transformer coupling,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 1933–1941, Sep. 2007.
    [32] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, and M.-H. Juang, “A low-voltage quadrature CMOS VCO based on voltage-voltage feedback topology,” IEEE Microw. Wireless Compon. Lett., vol. 16, no.12, pp. 696–698, Dec. 2006.
    [33] C. T. Fu and H. C. Luong,” A 1V CMOS quadrature LC VCO using diode coupling,” IEEE Radio and Wireless Symposium, pp.167-170, 2008.
    [34] S.-L. Jang, Y.-K. Wu, C.-C. Liu and J.-F. Huang, ” A dual-band CMOS voltage-controlled oscillator implemented with dual-resonance LC tank,” IEEE Microw. Wireless Compon. Lett., vol. 19, No. 12, pp.816-818, Dec. 2009.
    [35] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
    [36] H. Wu and L. Zhang, “A 16-to-18GHz 0.18μm epi-CMOS divide-by-3 injection-locked frequency divider, ” IEEE Int. Solid-State Circuits Conf., Feb. 2006, pp. 602–603.
    [37] S.-L. Jang, C.-F. Lee, and W.-H. Yeh, “A divide-by-3 injection locked frequency divider with single-ended input,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 2, pp. 142–144, Feb. 2008.
    [38] L.-H. Lu, H.-H.Hsieh, and Y.-T. Liao, “A wide tuning-range CMOS VCO with a differential tunable active inductor,” IEEE Trans. Microw. Theory Tech., vol. 45, no. 9, pp. 3462–3468, Sept. 2006.
    [39] S.-L. Jang, C. C. Liu, and C.-W. Chung, “A Tail-injected divide-by-4 SiGe HBT injection locked frequency divider,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 4, pp. 236–238, Apr. 2009.
    [40] C.L. Ler, A.K.B. A’ain and A.V. Kordesh, “CMOS source degenerated differential active inductor,” IEEE Electron. Lett., vol. 44, no. 3, pp. 196–197, Jan. 2008.
    [41] S.-L. Jang, J.-C. Han, C.-F. Lee, and J.-F. Huang, “A small die area and wide locking range CMOS frequency divider,” Microwave and Optical Technology Lett., vol. 50, no. 2, pp. 541–544, Feb. 2008.
    [42] S.-L. Jang, C.-C. Liu, and J.-F. Huang, “A wide locking range quadrature injection locked frequency divider with tunable active inductor,” IEICE Trans. Electron., vol.E91-C, no. 3, pp. 373–377, Mar. 2008.
    [43] S.-L. Jang, C.-W. Tai, and C.-F. Lee, “Divide-by-3 injection locked frequency divider implemented with active inductor,” Microwave and Optical Technology Lett., vol. 50, no. 6, pp.1682–1685, June, 2008.
    [44] R. Kaunisto, P. Alinikula, K. Stadius, and V. Porra, “A low-power HBT MMIC filter based on tunable active inductors,” IEEE Microwave and Guided Wave Lett., vol. 7, no. 8, pp. 209–211, Aug. 1997.
    [45] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-um CMOS technology,” Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2003, pp. 259–262.
    [46] W.-Z. Chen, W.-H. Chen and K.-C. Hsu, “3-dimensional fully symmetric inductors, transformer, and balun in CMOS technology”, IEEE Trans. Circuits and Systems – I, vol. 54, no. 7, pp. 1413-1423, July 2007.
    [47] S.-L. Jang, C.-W. Chang, C.-F. Lee, and J.-F. Huang, ” Divide-by-3 LC injection locked frequency divider implemented with 3D inductors,” IEICE Trans. Electronics., vol. E91-C, no. 6, pp. 956-962, Jun. 2008.
    [48] S.-L. Jang, Y.-J. Wu, C.-F. Lee and M.-H. Juang, ” A Clapp LC-tank injection locked frequency divider,” Microw. and Optical Tech. Lett., vol. 49, no. 11, pp. 2625-2628, Aug. 2007.
    [49] S.-L. Jang, M.-H. Suchen, and C.-F. Lee, ” Colpitts injection locked frequency divider implemented with a 3D helical transformer ,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 6, pp. 410-412, June, 2008.
    [50] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: Oxford Univ. Press, 1999.
    [51] B. Razavi, Design of Analog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.

    無法下載圖示 全文公開日期 2015/07/26 (校內網路)
    全文公開日期 本全文未授權公開 (校外網路)
    全文公開日期 本全文未授權公開 (國家圖書館:臺灣博碩士論文系統)
    QR CODE