本論文研究為應用於第五代行動通訊之可程式增益放大器。本研究所使用的可程式放大器，使用了衡定電流之架構以改變電路輸入端之電晶體大小的方式來改變增益。而為了增加整體電路的線性度，本架構使用源級退化電阻來改善電路。本研究所設計的程式放大器運用四組可程式增益放大器子電路串聯並且由5-bit 二進為編碼所控制，第一級子電路將提供 -16 dB的衰減來處理，而二至四級電路，每級將提供7 dB的可程式增益範圍，當每次進行1-bit控制碼的增減，輸出訊號的增益將因此增加或減少1 dB，而電路將提供總共 20 dB的可程式增益範圍，可將電路的輸出增益控制在-16 dB 至 4 dB 之間。
本論文包含兩個晶片，第一個晶片為單獨於TSMC 40 nm所下線的可程式增益放大器電路，其操作電壓為1.3 V，功率消耗為21.8 mW。在50歐姆的量測環境下，可控制增益範圍為 -40.85 dB 至 -20.5 dB，而頻寬在可控制增益範圍內為1.02 GHz 到 1 GHz。而在可程式增益範圍內，增益階的增益誤差為 0.83 dB
。
第二個晶片為加上低通濾波器後所完成的發射端類比基頻電路系統，下線的製程為為TSMC 90 nm。在其操作電壓為1.2 V，功率消耗為93 mW，在50歐姆的量測環境下，可控制增益範圍為 -39.67 dB 至 -16.26 dB，而頻寬在可程式增益範圍內為1.03 GHz 到 1.05 GHz。而在可程式範圍內，增益誤差為 1.1 dB。

A wideband programmable gain amplifier (PGA) in a transmitter for fifth generation communication (5G) is presented in this thesis. A constant current structure with linearization techniques would be used to improve the performances of gain error, 3-dB bandwidth, and linearity. The structure of PGA consists of four gain cells in cascade to provide 20 gain steps. The PGA would cover the dB-linear gain range from -16 dB to 4 dB where the gain can be varied in 1-dB step.
The stand-alone 5-bit PGA is fabricated in TSMC 40-nm CMOS process. The measured gain control range with 50-Ω network analyzer is from -40.85 dB to -20.5 dB. The 3-dB frequency range is from 1.02 GHz to 1 GHz. The 1-dB gain step error is less than  0.83 dB and the power consumption is 21.8 mW under 1.3 V supply voltage.
In this work, a TX analog baseband is consisted of PGA and (low pass filter) LPF. The TX analog baseband is fabricated in TSMC 90-nm CMOS process. The measured gain control range with 50-Ω network analyzer is from -39.67 dB ~ -16.26 dB .The 3-dB frequency range is from 1.03 GHz to 1.05 GHz. The 1-dB gain step error is less than  1.1 dB and total power consumption of TX analog baseband is 93 mW under 1.2 V supply voltage.

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