本篇論文提出兩個類比記憶體之研究主題，以使用台積電 0.35 微米 2P4M 互補式金氧半導體製程為主，第一部分提出快速類比記憶體編成之積體電路與系統，可以透過改良後之編程系統對懸浮閘上之非揮發性電荷進行快速編程。第二部分提出一個具有功率調節之緩衝放大器，運用第一部分之類比記憶體技術，將緩衝放大器達成可因應不同之需求進行可重組之變化，以符合在不同使用情境之需求，並用超級 AB 類之架構去應對在輸入訊號之劇烈變化下，能產生自動調節功率之能力。

為了滿足在編程時可能因懸浮閘電晶體之數量過多，而導致在編程上會花費許多時間，為了改善可能在熱載子注入時之負壓無法快速回升之現象，本文提出一個具有能調節負壓高低與快速回穩之負壓電荷幫浦電路，能達成在 5 微秒 之內回到穩定，相比原本所使用之負電荷幫浦電路需花費 500 微秒 才能穩定。並且使用了穩壓負電荷幫浦電路，利用負回授機制將負壓透過電阻分壓的方式調節負壓深淺。在原先之編程系統所使用晶片外之數位類比轉換器、類比數位轉換器、可編程邏輯陣列與個人電腦。為了更進一步縮短編程時間，在開發軟體上進行修改，並減少 MATLAB 傳遞時間，使所有控制訊號均由可編程邏輯陣列中之微處理器來達成所有需求。如此一來，編成一顆類比記憶體平均只需要 10 毫秒。

為了能有效降低在生醫應用上之功率消耗，本篇論文提出一個適用於低功耗類比前端電路中之緩衝放大器，藉由前者所使用之懸浮閘電晶體編程技術，可達成在生理訊號中不同頻域上之需求變化。在選擇電路架構上，使用了全電容回授之緩衝放大器並搭配懸浮閘所提供之可調節輸入直流準位以及消除輸入電壓之偏移。並且此緩衝放大器為了能有驅動晶片外之藍芽晶片，並以其藍芽晶片前端之類比數位轉換器的輸入電容值為負載考量。為了能確保擁有足夠之驅動能力用以推動後級，因此在放大器之設計架構上採用了二階組態之 AB 類架構達到應有之迴轉率。已在台積電下 0.35 微米 之 CMOS 製程實現，其面積為 0.151 毫米平方。量測結果上在後端為藍芽晶片之使用情境下，用以輸出負載為 10 pF 之下進行量測，在增益頻寬為 100 kHz 時其功率消耗為 3 µW，並量測輸入二階截取點為 52.66 dBV 與迴轉率為 7.86 V/ us。而為了測試其電路上能接受之最大輸出負載上並維持其應有足夠之相位裕度之下，用以輸出負載為 70 pF 之下進行量測，在增益頻寬為100 kHz 時其功率消耗為 3.05 uW，並量測輸入二階截取點為 50.9dBV 與迴轉率為2.97 V/ us。

This paper proposes two research topics on analog memory, mainly using TSMC 0.35 um 2P4M complementary metal oxide semiconductor process. The first part presents an integrated circuit and system based on fast analog memory, which can be programmed through an improved programming system. Fast programming of non-volatile charges on floating gates. The second part proposes a buffer amplifier with power adjustment; using the analog memory technology of the first part, the buffer amplifier can be reconfigured according to different needs to meet the needs of different usage scenarios and use the super AB class structure. To sense with the drastic changes in the input signal, it can produce the ability to adjust the power automatically.

To meet the requirement that it may take a lot of time to program due to the excessive number of floating thyristors during programming, in order to improve the phenomenon that the negative pressure may not be able to recover quickly during hot carrier injection, this paper proposes a method with adjustable negative pressure. The negative voltage charge pumps circuit with high and low voltage, and fast stabilization can achieve stability within 5 µs, compared to the original negative charge pump circuit that needs 500 µs to stabilize. And a regulated negative charge pump circuit is used, and a negative feedback mechanism is used to adjust the depth of the negative pressure by dividing the negative pressure through a resistor. Off-chip digital-to-analog converters, analog-to-digital converters, programmable logic arrays and personal computers used in previous programming systems. To further shorten the programming time, modify the development software and reduce the MATLAB transfer time so that all control signals are achieved by the micro-processor in the programmable logic array to accomplish all requirements. As a result, it only takes an average of 10 milliseconds to program an analog memory.

To effectively reduce the power consumption in biomedical applications, this paper proposes a buffer amplifier suitable for low-power analog front-end circuits. Using the floating thyristor programming techniques used in the former can be used in physiological signals. Demand changes in different frequency domains. In the selection circuit structure, a buffer amplifier with full capacitance feedback is used, and the adjustable input DC level provided by the floating gate is used to eliminate the offset of the input voltage. And this buffer amplifier can drive the bluetooth chip outside the chip, and the input capacitance value of the analog-digital converter at the front end of the bluetooth chip is considered a load. In order to ensure enough driving capability to drive the post-stage, the amplifier design structure adopts the class-AB structure of the second-order configuration to achieve the proper slew rate. It has been implemented in TSMC’s 0.35 um CMOS process with an area of 0.151 mm2. The back-end is used as a Bluetooth chip in the measurement results, and the output load is 10 pF. The power consumption is 3 uW when the gain bandwidth is 100 kHz, and the second-order input interception is measured. The point is 52.66 dBV, and the slew rate is 7.86 V/ us. In order to test the maximum output load that can be accepted on the circuit and maintains it with sufficient phase margin, the power consumption is measured when the output load is 70 pF, the gain bandwidth at 100 kHz is 3.05 uW, and the measured input second-order intercept point is 50.9 dBV, and the slew rate is 2.97 V/us.

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