研究生: |
莊帛縈 Po-Ying Chuang |
---|---|
論文名稱: |
選擇性成長自組裝單分子薄膜修飾薄膜電晶體元件線路之效應研究 Study on the Effect of Site‐Selective Growth of Self‐Assembled Monolayer on Thin-Film Transistors |
指導教授: |
何郡軒
Jinn-Hsuan Ho 戴龑 Yian Tai |
口試委員: |
劉舜維
Shun-Wei Liu 何郡軒 Jinn-Hsuan Ho 戴龑 Yian Tai |
學位類別: |
碩士 Master |
系所名稱: |
工程學院 - 化學工程系 Department of Chemical Engineering |
論文出版年: | 2019 |
畢業學年度: | 107 |
語文別: | 中文 |
論文頁數: | 116 |
中文關鍵詞: | 選擇性成長 、自組裝單分子薄膜 、薄膜電晶體 |
外文關鍵詞: | Site‐Selective Growth, SAM, TFT |
相關次數: | 點閱:265 下載:0 |
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此研究利用接觸角量測儀以及X光電子能譜儀驗證阻擋層對於圖案化ITO玻璃基板具有良好選擇性,從而有效阻止矽烷基團與ITO表面進行鍵結,而利用移除試劑移除後,電極功函數與原先之差異並不大。並探討兩種相反偶極方向之自組裝單分子薄膜,修飾在頂部閘極底部接觸式元件基板線路部分對薄膜電晶體造成的影響,並利用阻擋層在ITO電極上方覆蓋住以防止矽烷基鍵結在ITO汲/源電極上,造成電極功函數之改變而形成多餘的變異參數,而將拉電子基團與推電子基團分別應用於玻璃基板上,實驗結果發現其分別能增進不同種元件上的電洞與電子傳輸,進而達到優化元件的效果。
It remains a challenge to utilize silane based self-assembled monolayers (SAMs) to site‐selective growth to modify channel part of the top gate bottom contact (TGBC) configuration of organic thin film transistor (OTFT). As we know, if we want to modify the surface between the active layer and the substrate, the silane based SAMs will anchor onto the entire substrate, causing work function modulation of source and drain electrodes. Here we use blocking layer (SAM1) due to good selectivity between glass and ITO electrodes which only passivated on the ITO region, in this study we used SAM1 to avoid the silane group anchored onto ITO electrodes which would cause above problem. We utilize 3-cyanopropyltriethoxysilane (CN-silane) and (3-Aminopropyl)triethoxysilane (NH2-silane) to modified the channel part of patterned substrate. This research shows modified substrates were applied on p-type material, Poly(3-hexylthiophene) (P3HT), ambipolar polymer, diketopyrrolopyrrole (DPP) and oxide semiconductor, IGZO based transistors. Through our study, the performance of OTFT is correlated with the surface dipole moment of the interface which is between the substrate and active layer in the channel region, the electron withdrawing and donating groups in SAMs can improve the performance of the P-type and N-type semiconductor devices, respectively.
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