以FPGA平台實現時間轉換器這個領域已經發展了多年，由於近年來物聯網及環境感測器的需求的大幅成長，與該領域相關的研究又以以TDC電路為大宗，在輸出精確時間訊息的DTC電路由於應用上不如TDC豐富，因此對此研究的著墨較少。
工業應用上常用的ATE系統及BIST技術由於需要十分精準的參考時間源來實現可程式化的時序產生器，因此目前都需要將待側物以大型儀器進行測試。如何能將精準且可程式化的時序產生器微縮至系統甚至是晶片上就成為測試系統研發的重要課題。DTC電路能根據輸入的控制字組產生解析度為皮秒等級的不同時間差，是ATE系統產生時序延遲的核心技術之一。
在本論文中講述了兩種高精度DTC設計方法，兩者都利用PLL負迴授的特性控制各級延遲量在各種變異下的均一性，目的是在於提升解析度並讓效能更加穩定，使FPGA應用得以更進一步與類比設計匹敵。本論文使用Altera Stratix IV平台所實現的鎖相迴路延遲環繞矩陣法DTC可達到最高5.2 ps之時間解析度，且其差分非線性誤差(DNL)、積分非線性誤差(INL)及輸出抖動表現分別只有 -2.3 ~ 2.4 LSB、 -1.8 ~ 1.8 LSB及2.3 LSB，比現極為出色。使用 Xilinx Virtex-6平台實現的精密相位偏移控制法DTC可達到最高14.8 ps之時間解析度，且DNL、INL及輸出抖動表現分別為 -0.6 ~ 0.8 LSB、 -0.4 ~ 0.7 LSB及0.8 LSB ，預計將對ATE系統與BIST的研發產生極大助益。

Timing Converter has been developed for quite many years due to the increasing demand of Internet-of-Things (IoT) and environmental sensors. However, the focus on the related field is always on Time-to-Digital Converter (TDC) design. The research on Digital-to-Time Converter (DTC) design which can generate precise timing information is not as popular as TDC.
In the industry, Automatic Test Equipment (ATE) and Built-In Self-Test (BIST) technology are commonly used. Both of them need a high precision reference clock and a programmable timing generator. Usually, they need some bulky instruments for support. Delay timing generation is a critical feature for ATE or BIST. The accurate programmable delay generator such as DTC can be the first developed core of miniature ATE on a system or BIST on a single chip.
In this thesis, a precise phase division DTC, or digital pulse generator, based on phase-locked loop (PLL) delay matrix is proposed to further extend FPGA applications into the analog domain. Most delay elements in delay matrix are controlled by PLLs so that output phases are uniformly distributed within reference clock period. For concept proof and proposal evaluation, the proposed DTC based PLL delay matrix is implemented with Altera Stratix IV FPGA and the achieved resolution is as high as 5.2ps with -2.3 ~ 2.4 LSB differential nonlinearity (DNL), -1.8 ~ 1.8 LSB integral nonlinearity (INL) and 2.3 LSB jitter performance respectively. Another realized DTC with much simpler structure based on fine-phase shift control is implemented on Xilinx Virtex-6 FPGA. A 14.8ps resolution is accomplished with -0.6 ~ 0.8 LSB DNL, -0.4 ~ 0.7 LSB INL and 0.8 LSB jitter performance. It will substantially benefit the development of ATE and BIST.

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