在半導體的先進製程中，對準誤差量測技術(Overlay Metrology)為關鍵的製程步驟，準確地測量出積體電路層與層之間的對準誤差(Overlay)，可以有效減少製程的重工率進而降低製程成本。DBO(Diffraction Based Overlay)技術因為擁有多項優點，被視為最具淺力的對準誤差量測方法之一，由於DBO量測技術是根據不對稱的反射繞射光計算對準誤差，因此可以縮小專用的對準符號，將其放置於積體電路中進行量測，此技術稱為μDBO，是次十奈米製程節點中備受期待的重要技術，然而μDBO的對準符號相當容易受到製程的破壞導致量測出現明顯的誤差，因此無法應用於尚未開發完成的製程當中。本研究主要針對μDBO對準符號具有底層光柵不對稱的側壁角(Asymmetric Side-Wall Angle)的情形進行分析與改善，藉由結合嚴格耦合波分析(Rigorous Coupled Wave Analysis, RCWA)與光柵繞射定理大量模擬μDBO實際量測的瞳孔影像(Pupil Image)，並以此作為數據集，通過二維雙向主成份分析技術(Two-Directional Two-Dimensional PCA)提取數據集中重要的特徵後，匯入BP神經網絡(Back Propagation Neural Network)中訓練網絡各層的權重等參數，以建立對準誤差校正模型，可在不通過傳統的μDBO計算公式之下，預測出準確的對準誤差。本研究分析的對準符號共有40種，產生的模擬資料共25200筆，每個對準符號對應的模型皆重複測試10次，對測試集預測的結果之均方誤差(Mean Square Error, MSE)平均為3.66E-10，而以μDBO原理計算的對準誤差之均方誤差平均約為2.508，成功地改善對準符號具有底層光柵不對稱的側壁角所引起的量測誤差，有效增強μDBO量測的準確度。

Overlay metrology is a crucial process in the advanced process nodes of semiconductor manufacturing. Accurately measuring the overlay between the process layers effectively reduces the rework rate. Diffraction based overlay (DBO) is regarded as a critical overlay metrology technique, it can place the dedicated overlay targets in the wafer fields for measurement, this technique is called μDBO. However, the μDBO overlay target is quite vulnerable to the destruction of the process leading to significant errors in the measurement. This study focuses on the analysis and improvement of the case where the μDBO overlay targets have an existed asymmetric side-wall angle (ASWA) in the underlying grating. This thesis proposes to use rigorous coupled wave analysis (RCWA) based on the diffraction theory to simulate numerous pupil images, and then input it to BP network for training after extracting important features via two-directional two-dimensional PCA from the images. Finally, the author establishes an new overlay model. This model can predict accurate overlay without using the traditional μDBO calculation formula. There are 40 types of overlay targets analyzed in this study, and a total of 25,200 simulation data generated. The overlay model corresponding to each overlay target is tested repeatedly for 10 times. The mean square error (MSE) for the prediction results of the test set is 3.66e-10 in average but the average overlay MSE based on the conventional μDBO formula is approximately 2.508. The estimation error caused by the ASWA in the underlying grating of overlay target is successfully improved by the proposed overlay model, and the accuracy of the μDBO measurement is effectively enhanced.

[1] R. R. Schaller, "Moore's law: past, present and future," IEEE spectrum, vol. 34, pp. 52-59, 1997.
[2] "International Technology Roadmap for Semiconductors 2.0 Report,"ed. 2013.
[3] A. J. den Boef, "Optical wafer metrology sensors for process-robust CD and overlay control in semiconductor device manufacturing," Surface Topography: Metrology and Properties, vol. 4, p. 023001, 2016.
[4] "The international technology roadmap for semiconductors,"ed.2017.
[5] C. Ludwig and S. Meyer, "Double patterning for memory ICs," in Recent Advances in Nanofabrication Techniques and Applications, ed: InTech, 2011.
[6] S. Hsu, R. Howell, J. Jia, H.-Y. Liu, K. Gronlund, S. Hansen, et al., "EUV resolution enhancement techniques (RETs) for k 1 0.4 and below," in Extreme Ultraviolet (EUV) Lithography VI, 2015, p. 94221I.
[7] H. J. Levinson, "Lithography and mask challenges at the leading edge," in Photomask Technology 2015, 2015, p. 963502.
[8] N. Aung, W. J. Chung, P. Samudrala, H. Gao, W. Gao, D. Brown, et al., "Overlay control for 7nm technology node and beyond," in Optical Microlithography XXXI, 2018, p. 105870A.
[9] J. Mulkens, B. Slachter, M. Kubis, W. Tel, P. Hinnen, M. Maslow, et al., "Holistic approach for overlay and edge placement error to meet the 5nm technology node requirements," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 105851L.
[10] F. Dettoni, R. Bouyssou, C. Dezauzier, J. Depre, S. Meyer, and C. Prentice, "Enhanced 28nm FD-SOI diffraction based overlay metrology based on holistic metrology qualification," in Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, p. 101452B.
[11] B. Schulz, R. Seltmann, J. Busch, F. Hempel, E. Cotte, and B. Alles, "Meeting overlay requirements for future technology nodes with in-die overlay metrology," in Metrology, Inspection, and Process Control for Microlithography XXI, 2007, p. 65180E.
[12] S. Lucarini, B. Dirahoui, R. Hafer, W. Weng, L. Safran, S. Pendyala, et al., "The 28th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2017) May 15-18, 2017–Saratoga Springs, New York 12-May-17."
[13] B. M. Barnes, R. M. Silver, S. Schmucker, H. Zhou, M.-A. Henn, and M. Y. Sohn, "Extensibility of optics-based metrology for sub-5nm technology (Conference Presentation)," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 1058504.
[14] O. Inoue, Y. Okagawa, K. Hasumi, C. Shao, P. Leray, S. Halder, et al., "SEM based Overlay measurement between Resist and buried patterns," in Metrology, Inspection, and Process Control for Microlithography XXX, 2016, p. 97781D.
[15] K. Hasumi, O. Inoue, Y. Okagawa, C. Shao, P. Leray, S. Halder, et al., "SEM-based overlay measurement between via patterns and buried M1 patterns using high-voltage SEM," in Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, p. 101451J.
[16] J. Xu, L. Qin, Q. Chen, H. Zhi, Y. Wang, Z. Yang, et al., "Diffraction-based and image-based overlay evaluation for advanced technology node," in Semiconductor Technology International Conference (CSTIC), 2017 China, 2017, pp. 1-4.
[17] H. L. Hsu, E. C. Lio, C. Chen, J. H. Chang, S. S. Lee, S. Buhl, et al., "Advanced combined overlay and CD uniformity measurement mark for double patterning," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018.
[18] L. Ye, H. Hu, and W. He, "Image-based overlay (IBO) target segment design on self-aligned patterning process," in Metrology, Inspection, and Process Control for Microlithography XXX, 2016, p. 977828.
[19] Y. Blancquaert, C. Dezauzier, J. Depre, M. Miqyass, and J. Beltman, "Performance of ASML YieldStar μDBO overlay targets for advanced lithography nodes C028 and C014 overlay process control," in Metrology, Inspection, and Process Control for Microlithography XXVII, 2013, p. 86811F.
[20] P. Leray, "Metrology challenges for in-line process control," in Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, p. 1014503.
[21] K. Bhattacharyya, A. den Boef, M. Jak, G. Zhang, M. Maassen, R. Tijssen, et al., "Holistic approach using accuracy of diffraction-based integrated metrology to improve on-product performance, reduce cycle time, and cost at litho," in Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 94241E.
[22] K. Bhattacharyya, A. den Boef, M. Noot, O. Adam, G. Grzela, A. Fuchs, et al., "A complete methodology towards accuracy and lot-to-lot robustness in on-product overlay metrology using flexible wavelength selection," in Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, p. 101450A.
[23] T. Shapoval, J. Engelmann, C. Kroh, N. Schmidt, S. Agarwal, R. Ramkhalawon, et al., "Etch process monitoring possibilities and root cause analysis," in Advanced Semiconductor Manufacturing Conference (ASMC), 2016 27th Annual SEMI, 2016, pp. 419-422.
[24] S. Lozenko, T. Shapoval, G. Ben-Dov, Z. Lindenfeld, B. Schulz, L. Fuerst, et al., "Matching between simulations and measurements as a key driver for reliable overlay target design," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 105851E.
[25] B. Bunday, A. Bello, E. Solecky, and A. Vaid, "7/5nm logic manufacturing capabilities and requirements of metrology," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 105850I.
[26] F. Dettoni, T. Shapoval, R. Bouyssou, T. Itzkovich, R. Haupt, and C. Dezauzier, "Image based overlay measurement improvements of 28nm FD-SOI CMOS front-end critical steps," in Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, p. 101450C.
[27] H.-J. H. Smilde, R. J. van Haren, W. van Buël, L. H. Driessen, J. Dépré, J. Beltman, et al., "Target design optimization for overlay scatterometry to improve on-product overlay," in Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 942412.
[28] Y.-S. Kim, Y.-S. Hwang, M.-R. Jung, J.-H. Yoo, W.-T. Kwon, K. Ryan, et al., "Improving full-wafer on-product overlay using computationally designed process-robust and device-like metrology targets," in Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 942414.
[29] B. Bringoltz, T. Marciano, T. Yaziv, Y. DeLeeuw, D. Klein, Y. Feler, et al., "Accuracy in optical overlay metrology," in Metrology, Inspection, and Process Control for Microlithography XXX, 2016, p. 97781H.
[30] Y. Zhou, D. Park, K. Gutjahr, A. Gottipati, T. Vuong, S. Y. Bae, et al., "Reducing the overlay metrology sensitivity to perturbations of the measurement stack," in Metrology, Inspection, and Process Control for Microlithography XXXI, 2017, p. 101452G.
[31] N. Padmavathi, "Comparative study of kernel SVM and ANN classifiers for brain neoplasm classification," in Intelligent Computing, Instrumentation and Control Technologies (ICICICT), 2017 International Conference on, 2017, pp. 469-473.
[32] M. S. Roy, R. Gupta, J. K. Chandra, K. D. Sharma, and A. Talukdar, "Improving Photoplethysmographic Measurements Under Motion Artifacts Using Artificial Neural Network for Personal Healthcare," IEEE Transactions on Instrumentation and Measurement, pp. 1-10, 2018.
[33] H. Zhang, C. Cao, L. Xu, and T. A. Gulliver, "A UAV Detection Algorithm Based on an Artificial Neural Network," IEEE Access, vol. 6, pp. 24720-24728, 2018.
[34] N. Jia and E. Y. Lam, "Machine learning for inverse lithography: using stochastic gradient descent for robust photomask synthesis," Journal of Optics, vol. 12, p. 045601, 2010.
[35] X. Ma, X. Zhao, Z. Wang, Y. Li, S. Zhao, and L. Zhang, "Fast lithography aerial image calculation method based on machine learning," Applied Optics, vol. 56, pp. 6485-6495, 2017.
[36] H.-F. Kuo and A. Faricha, "Artificial Neural Network for Diffraction Based Overlay Measurement," IEEE Access, vol. 4, pp. 7479-7486, 2016.
[37] P. Leray, "Conference 10145: Metrology, Inspection, and Process Control for Microlithography XXXI," in San Jose Marriott and San Jose Convention Center San Jose, California, USA Conferences & Courses 26 February–2 March 2017, p. 46.
[38] M. Overcast, C. Mellegaard, D. Daniel, B. Habets, G. Erley, S. Guhlemann, et al., "Understanding overlay signatures using machine learning on non-lithography context information," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 105851U.
[39] T. Nakazawa and D. V. Kulkarni, "Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network," IEEE Transactions on Semiconductor Manufacturing, vol. 31, pp. 309-314, 2018.
[40] J. Maas, M. Ebert, K. Bhattacharyya, H. Cramer, A. Becht, S. Keij, et al., "YieldStar: a new metrology platform for advanced lithography control," in 27th European Mask and Lithography Conference, 2011, p. 79850H.
[41] S. C. Hsu, Y. C. Pai, C. Chen, C. C. Yu, H. Hsing, H.-C. Wu, et al., "Scatterometry or imaging overlay: a comparative study," in Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 942409.
[42] Prasad Dasari, Jie Li, Jiangtao Hu, Nigel Smith, Oleg Kritsun, et al., "Diffraction Based Overlay Metrology for Double Patterning Technologies," in Proceedings of the SPIE, 2009, p. 727212.
[43] S. Heidenreich, M.-A. Henn, H. Gross, B. Bodermann, and M. Bär, "Alternative methods for uncertainty evaluation in EUV scatterometry," in Modeling Aspects in Optical Metrology IV, 2013, p. 87890T.
[44] V. Calado, J. Dépre, C. Massacrier, S. Tarabrin, R. van Haren, F. Dettoni, et al., "Study of μDBO overlay target size reduction for application broadening," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 1058507.
[45] M. Ebert, P. Vanoppen, M. Jak, G. vd Zouw, H. Cramer, T. Nooitgedagt, et al., "New approaches in diffraction based optical metrology," in Metrology, Inspection, and Process Control for Microlithography XXX, 2016, p. 97782N.
[46] T.-S. Kim, Y.-S. Park, Y.-C. Kim, B.-H. Kim, J.-H. Lee, M.-K. Kwak, et al., "Improved control of multi-layer overlay in advanced 8nm logic nodes," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 1058527.
[47] H.-J. H. Smilde, R. J. van Haren, W. van Buël, L. H. Driessen, J. Dépré, J. Beltman, et al., "Target design optimization for overlay scatterometry to improve on-product overlay," in Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 942412.
[48] O. D. S. Ferreira, R. S. Gousheh, B. Visser, K. Lie, R. Teuwen, P. Izikson, et al., "Holistic metrology qualification extension and its application to characterize overlay targets with asymmetric effects," in Metrology, Inspection, and Process Control for Microlithography XXXII, 2018, p. 105850T.
[49] J. Benschop, A. Engelen, H. Cramer, M. Kubis, P. Hinnen, H. van der Laan, et al., "Integrated scatterometry for tight overlay and CD control to enable 20-nm node wafer manufacturing," in Optical Microlithography XXVI, 2013, p. 86830P.
[50] H. Lee, B. Lee, S. Han, M. Kim, W. Kwon, S. Park, et al., "Overlay accuracy investigation for advanced memory device," in Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 94240C.
[51] H. Lee, B. Lee, S. Han, M. Kim, W. Kwon, S. Park, et al., "Overlay measurement accuracy enhancement by design and algorithm," in Metrology, Inspection, and Process Control for Microlithography XXIX, 2015, p. 94242B.
[52] J. Mulkens, M. Kubis, P. Hinnen, R. de Graaf, H. van der Laan, A. Padiy, et al., "High order field-to-field corrections for imaging and overlay to achieve sub 20-nm lithography requirements," in Optical Microlithography XXVI, 2013, p. 86831J.
[53] K.-H. Chen, G. Huang, K. Chen, C. Hsieh, Y. Chen, C. Ke, et al., "Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)," in Metrology, Inspection, and Process Control for Microlithography XXVIII, 2014, p. 90500S.
[54] K. Bhattacharyya, A. den Boef, G. Storms, J. van Heijst, M. Noot, K. An, et al., "A study of swing-curve physics in diffraction-based overlay," in Metrology, Inspection, and Process Control for Microlithography XXX, 2016, p. 97781I.
[55] M. Moharam, E. B. Grann, D. A. Pommet, and T. Gaylord, "Formulation for stable and efficient implementation of the rigorous coupled-wave analysis of binary gratings," JOSA a, vol. 12, pp. 1068-1076, 1995.
[56] J. Kennedy, "Particle swarm optimization," in Encyclopedia of machine learning, ed: Springer, 2011, pp. 760-766.
[57] C. A. C. Coello, G. T. Pulido, and M. S. Lechuga, "Handling multiple objectives with particle swarm optimization," IEEE Transactions on evolutionary computation, vol. 8, pp. 256-279, 2004.
[58] B. Moore, "Principal component analysis in linear systems: Controllability, observability, and model reduction," IEEE transactions on automatic control, vol. 26, pp. 17-32, 1981.
[59] D. Zhang, Z. Zhou, "(2D)2 PCA: Two-Directional Two-Dimensional PCA for Efficient Face Representation and Recognition", Neurocomputing, vol. 69, no. 1, pp. 224-231, 2005.
[60] D. Stathakis, "How many hidden layers and nodes?," International Journal of Remote Sensing, vol. 30, pp. 2133-2147, 2009.