本研究探討利用化學氣相沉積系統於二氧化矽/矽基板上成長二硫化鉬薄膜並分析其光電特性實驗中。分別利用熱蒸氣沉積以及熱蒸氣硫化兩種成長方法製備二硫化鉬薄膜。熱蒸氣沉積製備方法為將三氧化鉬粉末與硫粉在高溫下產生蒸氣反應形成二硫化鉬薄膜。此方法在硫不足量時會有硫化不完全的情形。蒸氣端與基板垂直距離1公分時會成長出具有導電性的氧硫化鉬(MoO1-xSx)化合物;蒸氣端水平距離17公分能成長出約4層的二硫化鉬薄膜，但是附著性不佳。有鑑於該薄膜無法進一步運用於元件製程，本研究另嘗試熱蒸氣硫化製備二硫化鉬薄膜，利用直流磁控濺鍍系統先在基板上成長厚度為1奈米之鉬薄膜，接著在高溫下進行硫化形成二硫化鉬薄膜。該製備在硫化壓力500 torr、時間20分鐘、溫度1000 °C可成長品質較好的二硫化鉬薄膜。樣品由拉曼光譜解析，A1g與E12g譜峰差約為24.5 cm-1，薄膜約為5層薄膜厚度;由室溫光激螢光光譜解析，主要存在可能受硫空位缺陷的施體型束縛激子A(bound exciton, BX)及自由激子B(free exciton, FX)。束縛激子與自由激子譜峰能量分別為1.84 及1.98 eV。透過原子力掃描影像發現二硫化鉬薄膜表面存在三角形與六角形島狀結構，X光光電子能譜中的肩峰顯示鉬與硫可能有不同的鍵結，因此可能有缺陷存在。最後試著將品質較好的二硫化鉬薄膜製作成背閘極式電晶體，經由量測IDS-V¬DS關係圖發現，改變閘極偏壓可調變IDS，已具備電晶體功能。在閘極偏壓高於0 V，IDS在V¬DS=0 V時，仍存在電流，推測為二硫化鉬薄膜內部缺陷如硫空位缺陷造成旁路通道貢獻之電流。

This study presents a process for growth of Molybdenum disulfide (MoS2) thin films on SiO2/Si by chemical vapor deposition. Research included growth and optoelectronics characterizations of MoS2 from two different preparations. One is thermal vapor deposition (TVD) by MoO3 powder, another one is thermal vapor sulfurization (TVS) by sputtering Mo film. TVD preparation of MoS2 by MoO3 powder possibly occur incomplete sulfurization. This preparation can adjust the vertical distance to grow MoO1-xSx, and adjust horizontal distance can grow 4 monolayers MoS2 thin films but bad adhesion. TVS preparation of MoS2 by sputtering 1 nm Mo film can grow better quality at sulfurization pressure of 500 torr, time of 20 min, temperature of 1000 °C. The optical property of MoS2 thin film analyze by Raman spectroscopy and photoluminescence (PL). Results of Raman spectroscopy indicate the frequency difference of A1g and E12g is 24.5 cm-1, which means 5 monolayers thin films. PL shows bound exciton A and free exciton B energy is 1.84 and 1.98 eV. AFM image on the surface of MoS2 thin films shows the triangle and hexagonal island. XPS shows the shoulder peak which means another binding in MoS2 thin film. Finally, the back gate MoS2 transistor was prepared for checking electrical property. IDS-VDS curve indicate the transistor can work by gate control. For VGS>0, V¬DS=0, generating gating current. We assume the S vacancies formed a bypass channel result in the current.

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