Due to the strong demand in the market for the growth of massive storage
capacity, the density of NAND ash memory has been improved in terms of
scaling technology node, storing multi-bit per cell, and stacking layers ver-
tically. However, the three techniques also degrade read performance and
reliability signi_cantly. The long read latency comes from the increased data
sensing time and time-consuming ECC decoding time. Storing multiple bit
per cell results in more read reference voltages and increased latency of iden-
tifying the appropriate threshold voltages of memory cells. To address the re-
liability issue, low-density parity-check code (LDPC) is widely used on ash
memory to provide stronger error correction capability. However, LDPC
would introduce a long decoding latency when bit errors are numerous. In
this work, a coupled data storage (CDS) strategy is proposed to improve the
read performance of 3-D NAND Flash-memory storage devices. The pro-
posed CDS strategy supports two modes to improve read latency: The high
read-speed mode is designed to improve data sensing time with reduced volt-
age states, while the data correction mode is designed to mitigate bit errors
as well as LDPC overhead. Experiment results showed that the proposed
CDS strategy could reduce 50_66% read latency and 25_28% write latency
under the high read-speed mode. For the data correction mode, the RBER
could be decreased by 37~52% and the lifetime could be prolonged to 1.6 to
3 times on average.

Due to the strong demand in the market for the growth of massive storage
capacity, the density of NAND ash memory has been improved in terms of
scaling technology node, storing multi-bit per cell, and stacking layers ver-
tically. However, the three techniques also degrade read performance and
reliability signi_cantly. The long read latency comes from the increased data
sensing time and time-consuming ECC decoding time. Storing multiple bit
per cell results in more read reference voltages and increased latency of iden-
tifying the appropriate threshold voltages of memory cells. To address the re-
liability issue, low-density parity-check code (LDPC) is widely used on ash
memory to provide stronger error correction capability. However, LDPC
would introduce a long decoding latency when bit errors are numerous. In
this work, a coupled data storage (CDS) strategy is proposed to improve the
read performance of 3-D NAND Flash-memory storage devices. The pro-
posed CDS strategy supports two modes to improve read latency: The high
read-speed mode is designed to improve data sensing time with reduced volt-
age states, while the data correction mode is designed to mitigate bit errors
as well as LDPC overhead. Experiment results showed that the proposed
CDS strategy could reduce 50_66% read latency and 25_28% write latency
under the high read-speed mode. For the data correction mode, the RBER
could be decreased by 37~52% and the lifetime could be prolonged to 1.6 to
3 times on average.

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