首先，學生提出了一個低相位雜訊的CMOS壓控振盪器，其使用的是左手LC網路和一對開關式的可變電容。由台積電0.18μm製程晶片面積為0.435 0.809 。此晶片為雙頻帶，低頻(高頻)的可調範圍從3.85~4.29(6.063~6.374)GHz，可調電壓從0~1.1(1.1~2)V，在振盪頻率0(1.4)GHz下量測到的相位雜訊是-120.01/-120.17dBc/Hz，FOM為-187.0(-191.3)dBc/Hz。此篇論文使用了兩個單元的左手LC振盪器串聯並且讓LC振盪器並聯電路下方的交叉耦合以補償LC振盪器的損耗。
其次，學生提出了一個新型的四相位壓控振盪器(QVCO)，其電路包括了兩個基本型的交叉耦合電路並以一個尾電阻相接。並由台積電0.18μm製程晶片面積為0.825 0.712 。在供應電源0.9V之下，總功耗是2.77mW。可調頻率比有16.69%，可調範圍由6.15到7.27GHz可調電壓由0V到2V。量測相位雜訊-115.6dBc/Hz在6.15GHz下，其FOM為-186.9dBc/Hz.
最後，此篇論文是用實驗的方式來評估熱載子效應對RF特性的除三注入鎖定除頻器(ILFD)的影響。由台積電90nm製程，使用兩個nMOSFETs電晶體直接串聯注入一組n-core交叉耦合。而另一組p-core交叉耦合整流偏壓回n-core交叉耦合的body端。給予電壓應力的方式是將注入mos關閉，也就是只讓交叉耦合的部分受影響。最主要是為了觀察注入鎖定範圍的變化，其原因為利用加壓應力減少了注入鎖定除頻器的輸出擺幅所造成的結果。而熱載子效應會改變振盪器的頻率、功耗還有相位雜訊。

First,thethesis proposes a low phase noise CMOS voltage-controlled oscillator (VCO) using a left-handed (LH) LC network and a switching/tuning varactor pair. The proposed VCO has been implemented with the TSMC 0.18 μm 1P6M CMOS technology and the die area of the oscillator is0.435 × 0.809 mm2. The VCO can generate differential signals in the high (low)-band frequency range of 6.063~6.374(3.85~4.29) GHz.The measuredhigh (low)-band figure of merit (FOM) is -191.3 (-187.0)dBc/Hz. The VCO uses two units of left-handed LC resonator stacked in series, and the LC resonator is in shunt with a pair of cross-coupled transistors to compensate for the loss of LC resonator.

Secondly,the thesispresents a new quadrature voltage-controlled oscillator (QVCO), which consists of two cross-coupled voltage-controlled oscillators (VCOs) coupled via tail resistors. The proposed CMOS QVCO has beenimplementedwiththeTSMC 0.18 μm CMOStechnology and the die area is 0.825 × 0.712 mm2.At the supply voltage of 0.9 V, the total power consumption is 2.77 mW. The free-running frequency of the QVCO is tunable from 6.15GHz to 7.27GHz as the tuning voltage is varied from 0.0 V to 2 V. The measured phase noise is -115.6dBc/Hz at 1MHz frequency offset fromthe oscillation frequency of 6.15 GHz.

Finally, the thesisevaluates experimentally the RF characteristics of a wide-locking range divide-by-3 injection-locked frequency divider (ILFD) subjected to the hot carrier stress. The ILFD was implemented in the TSMC90nm CMOS process and it uses an n-core cross-coupled VCO with two direct injection nMOSFETs in series. Two p-core cross-coupled MOSFETs rectify dc voltage to bias the bodies of n-core cross-coupled transistors. High supply voltage stresses were applied at room temperature on the ÷3ILFD while the injection FETs are off. The main observed degradation is a decrease of locking range, which is attributed to reduced ILFD output voltage swing with stress. The hot-carrier stress shifts the oscillation frequency, power consumption and phase noise of free-running ILFD.

[1] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
[2] N. M. Nguyen, and R. G. Meyer, “Start-up and frequency stability in high-frequency oscillators,” IEEE J. Solid-State Circuits, vol. 27, no. 5, pp. 810−820, May 1992.
[3] B. Razavi, Design of Analog CMOS Integrated Crcuits, MC Graw Hall,2001.
[4] J. R. Long, “Monolithic transformers for silicon RF IC design," IEEE J.Solid-State Circuits, vol. 35, pp. 1368-1382, 2000.
[5] A .Zolfaghari, A. Chan, and B. Razavi, “Stacked inductors and transformers in CMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 620-628,2001.
[6] P. Andreani and S. Mattisson, “On the use of MOS varactors in RF VCOs,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 905−910, Jun. 2000.
[7] J. J. Rael and A. A. Abidi, “Physical processes of phase noise in differential LC Oscillators,” IEEE Custom Integrated Circuits Conference, 2000, pp. 569−572.
[8] T. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J. Solid-State Circuits, vol. 35, no. 3, pp. 326−336, Mar. 2000.
[9] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179−194, Feb. 1998.
[10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw Hill, 2001.
[11] D. Hauspie, E.-C. Park, and J. Craninckx, “Wide-band VCO with simultaneous switching of frequency band, active core, and varactor size,” IEEE J. Solid-StateCircuits, vol. 42, no. 7, pp. 1472–1480, Jul. 2007.
[12] P.-C. Huang, M.-D. Tsai, H. Wang, C.-H. Chen, and C.-S. Chang, “A 114GHz VCO in 0.13μm CMOS technology,” IEEE International Solid-State Circuits Conference, vol. 1, pp.404-606, 6-10 Feb. 2005.
[13] T. H. Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press 1998.
[14] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[15] H. Wu and A. Hajimiri, “A 19 GHz 0.5mW 0.35 μmCMOS frequency divider with shunt-peaking locking-range enhancement,” ISSCC Tech. Dig., Feb. 2001, pp. 412–413.
[16] J. Craninckx and M. S. J. Steyaert, “A 1.75-GHz/3-V dual-modulus divide-by- 128/129 prescaler in 0.7-μm CMOS,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 890−897, July 1996.
[17] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 456−463, Mar. 1996.
[18] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18-μm CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 594−601, Apr. 2004.
[19] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 813−821, Jun. 1999.
[20] H. D. Wohlmuth and D. Kehrer, “A high sensitivity static 2:1 frequency divider up to 27 GHz in 120 nm CMOS,” IEEE European Solid State Circuits Conference (ESSCIRC), Sept. 2002, pp. 823−826.
[21] M. Tiebout, “A 480 μW 2 GHz ultra low power dual-modulus prescaler in 0.25 μm standard CMOS,” IEEE International Symposium on Circuit and System (ISCAS), May 2000, vol. 5, pp. 741−744.
[22] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1 GHz and 2.8 GHz CMOS injection-locked ring oscillator prescalers,” IEEE Symposium on VLSI Circuits, Jun. 2001, pp.47−50.
[23] P. Kinget, R. Melville, D. Long, and V. Gopinathan, “An injection locking scheme for precision quadrature generation,” IEEE J. Solid-State Circuits, vol. 37, no. 7, pp. 845−851, Jul. 2002.
[24] W. Z. Chen and C. L. Kuo, “18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25 μm CMOS technology,” IEEE European Solid State Circuits Conference (ESSCIRC), Sept. 2002, pp. 89−92
[25] H. Wu, “Signal generation and processing in high-frequency/high-speed
silicon-based integrated circuits,” PhD thesis, California Institute of Technology, 2003.
[26] R. Adler, “A study of locking phenomena in oscillators,” Proc. IEEE, vol. 61, pp.1380-1385, Oct. 1973.
[27] A. Hajimiri and T. Lee, “Design issues in CMOS differential LC oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 717-724, May 1999.
[28] P. Andreani, X. Wang, L. Vandy, and A. Frad, “A study of phase noise in Colpitts and LC-tank CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1107-1118, May. 2005.
[29] S.-L. Jang, S. Jain, J.-F. Huang, and C.-W. Hsue ” DC-bias and oscillation-amplitude dependent frequency-tuning characteristics of varactor-switching dual-band CMOS VCOs,”vol. 55, No. 6, pp. 1389-1393, Microw. Opt. Technol. Lett., 2013.
[30] S.-L. Jang, Y.-J. Song, and C.-C. Liu,” A differential Clapp VCO in 0.13μm CMOS technology,” IEEE Microw. Wireless Compon. Lett., pp. 404-406, June, 2009.
[31] S.-L. Jang, Y.-K. Wu, C.-C. Liu and J.-F. Huang,” A dual-band CMOS voltage-controlled oscillator implemented with dual-resonance LC tank,”IEEE Microw. Wireless Compon. Lett., vol. 19, No. 12, pp.816-818, Dec. 2009.
[32] C. F. Chang, and T. Itoh, “A dual-band millimeter-Wave CMOS oscillator with left-handed resonator,” IEEE Trans. Microw.Theory Tech., vol. 58, no. 5, pp. 1401–1409, May 2010.
[33] B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE J. Solid-State Circuits, vol. 31, pp. 331 – 343, March 1996.
[34] D. Ham and A. Hajimiri, “Concepts and methods in optimization of integratedLC VCOs,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 896-909,Jun. 2001.
[35] X. Li, S. Shekhar, and D. J. Allstot, “Gm-boosted common-gate LNA and differential Colpitts VCO/QVCO in 0.18-μm CMOS,” IEEE J.Solid-State Circuits, vol. 40, no. 12, pp. 2609–2619, Dec. 2005.
[36] J.-A. Hou and Y.-H. Wang,“A 5 GHz differential Colpitts CMOS VCO using the bottom PMOS cross-coupled current source,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 6, pp. 401–403, Nov. 2009.
[37] J.-P. Hong and S.-G. Lee, “Low phase noise Gm-boosted differential gate-to-source feedback Colpitts CMOS VCO,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3079–3091, June 2009.
[38] J. Park, J. Park, Y. Choi, K. Sim and D. Baek, “A fully differential complementary Hartley VCO in 0.18μm CMOS technology”, IEEE Microw. Wireless Compon. Lett., vol. 20. no. 2, pp. 91–93, Feb. 2010.
[39] S. Kim, and H. Shin, “A 2.3-GHz sub-mW current-reuse CMOS VCO for wireless sensor node applications,” IEICE Trans. Electron., Vol.E95–C,pp.968-971, May 2012.
[40] J. Chen, F. Jonsson, M. Carlsson, C. Hedenas, and L.-R. Zheng, “A low power, startup ensured and constant amplitude Class-C VCO in 0.18um CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 8, pp. 427 –429, Aug. 2011.
[41] A. Mazzanti et al., "Injection locking LC dividers for lowpower quadrature generation", Custom Integrated CircuitsConference, 2003. Proceed. of the IEEE, pp. 563-566, Sep. 2003.
[42] J. Crols, M. Steyaert, "A fully integrated 900 MHz CMOSdouble quadrature down converter", IEEE Int. Solid-stateCircuits Conf. Dig. Tech. Papers, San Francisco, CA, pp.136-137, Feb. 1995.
[43] A. Rofougaran, J. Rael, M. Rofougaran, and A. Abidi, “A 900 MHz CMOS LC-oscillator with quadrature outputs,” in IEEE ISSCC Dig.Tech. Papers, Feb. 1996. pp. 392–393.
[44] H.-R. Kim, C.-Y. Cha, S.-M. Oh, M.-S. Yang, and S.-G. Lee, “A very low-power quadrature VCO with back-gate coupling,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 952–955, Jun. 2004.
[45] S. L. J. Gierkink, S. Levantino, R. C. Frye, C. Samori, and V. Boccuzzi, “A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1148–1154, Jul. 2003.
[46] S.-L. Jang, C.-C. Shih, C.-C. Liu, andM.-H. Juang, ” A 0.18 μm CMOS quadrature VCO using the quadruple push-push technique,” IEEE Microw. Wireless Compon. Lett., vol. 20, pp.343-345, June, 2010.
[47] S.-L. Jang, C.-C. Shih,C.-C. Liu,C.-W. Chang, and C.-W. Hsue,”CMOS quadrature VCOs using the varactor coupling technique,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 9, pp. 498-500, Sept. 2011.
[48] S. Gagliolo, G. Pruzzo, and D. D. Caviglia, "Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing", Proceed. of the 18th annual symp. Integrated circuits and system design, pp. 149-153, 2005.
[49] S. Milicevic and L. MacEachern, “Frequency of oscillation of a cross-coupled CMOS VCO with resistor tail biasing”, Proceed. of the 51stIEEE Midwest Symp. Circuits and Systems, Aug. 5-8, 2007.
[50] S. J. Yun, C. Y. Cha, H. C. Choi, and S. G. Lee, “RF CMOS LC-oscillator with source damping resistors,” IEEE Microwave and Components Letters, vol. 16, no. 9, pp. 511-513, Sept, 2006
[51] D. Ham and A. Hajimiri, “Concepts and methods in optimization of integratedLC VCOs,” IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 896-909,Jun. 2001.
[52] K.-W. Cheng,and M. Je, “A current-switching and gm–enhanced Colpitts quadrature VCO,” IEEE Microwave and Components Letters, vol. 23, no. 3, pp. 143-145, Mar., 2013.
[53] S. Y. Lee and C. Y. Chen, “Analysis and design of a wide-tuning-rangeVCO with quadrature outputs,” IEEE Trans. Circuits Syst. II, Exp. Briefs,vol. 55, no. 12, pp. 1209–1213, Dec. 2008.
[54] S. Y. Lee, L. H. Wang, and Y. H. Lin, “A CMOS Quadrature VCO withsubharmonic and injection-locked techniques,” IEEE Trans. Circuits Syst.II, Exp. Briefs, vol. 55, no. 11, pp. 843–847, Nov. 2010.
[55] Y. C. Chiang, T. F. Han, and H. H. Hsu, “Design of a CMOSquadratureVCO with current reuse method,” Microw. Opti. Technol. Lett., vol. 44, pp. 202–204, Feb. 2005.
[56] C. T. Fu and H. C. Luong, “A 0.8-V CMOS quadrature LC VCO usingcapacitive coupling,” in Proc. IEEE Asian Solid-State Circuits Conf.,2007, pp. 436–439.
[57] E. Takeda, Y. Nakagome, H. Kume, and S. Asai, “New hot-carrier injection and device degradation in submicron MOSFETs,” IEEE Proceed., vol. 130, no. 3, pp. 144-149, June 1983.
[58] J. T. Hsu, X. Li, and C. R. Viswanathan, “Low-frequency noise in short-channel MOSFETs degraded by Fowler-Nordheim and hot-carrierinjection,” Microelectronic Engineering, vol. 22, pp. 285-288, 1993.
[59] E. Simoen, P. Vasina, J. Sikula, and C. Claeys, “Empirical model for the low-frequency noise of hot-carrier degraded submicron LDD MOSFETs,” IEEE Electron Device Lett.,vol. 18, pp. 480-482, 1997.
[60] Z. Jin, J. D Cressler, W. Abadeer, X. Liu, M. Hauser, and A. J. Joseph, “Hot carrier stress induced low-frequency noise degradation in 0.13μm and 0.18 μm RF CMOS technologies,” IEEE Int. Reliability Physics Symp., 2004, pp. 440 – 444
[61] H.S. Momose, Y. Niitsu, H. Iwai, and K. Maeguchi, "Temperature dependence of emitter-base reverse stress degradation and its mechanism analyzed by MOS structures",IEEE Proceedings of the Bipolar Circuits and Technology Meeting, Paper 6.2, pp. 140-143, 1989.
[62] A. Neugroschel, C.-T. Sah, and M.S. Carroll, "Degradation of bipolar transistor current gain by hot holes during reverse emitter-base bias stress," IEEE Trans. Electron Devices, 43(8):1286-1290. 1996.
[63] J. T. Park, B.-J. Lee, D.-W. Kim, C.-G. Yu, and H.-K. Yu, “RF performancedegradation in nMOS transistors due to hot carrier effects,” IEEETrans. Electron Devices, vol. 47, no. 5, pp. 1068–1072, May 2000.
[64] W.Weber, L. Risch, W. Krautschneider, and Q. Wang, “Hot-carrier degradation of CMOS inverters,” Tech. Dig—Int. Electron Devices Meet., 208-211 (1988).
[65] T. Quemerais, L. Moquillon, V. Huard, J.-M. Fournier, P. Benech, N. Corraoand X Mescot, “Hot-carrier stress effect on a CMOS 65-nm 60-GHz one-stage power amplifier,”IEEE Electron Device Letters, 31, 9, 927-929, 2010.
[66] R. Adler, “A study of locking phenomena in oscillators,” Proc. IRE, vol.34, pp. 351–357, June 1946.
[67] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, “1-GHz and 2.8-GHzinjection-locked ring oscillator prescalers,” in Symp. VLSI Circuits Dig.Tech. Papers, June 2001, pp. 47–50.
[68] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency dividers,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004.
[69] S.-L. Jang, C.-F. Lee, and W.-H. Yeh, “A divide-by-3 injection locked frequency divider with single-ended input,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 2, pp. 142–144, Feb. 2008
[70] S.-L. Jang and C.-W Chang, “A 90nm CMOS LC-tank divide-by-3 injection locked frequency divider with record locking range,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 4, pp. 229–231, Apr. 2010.
[71] B. Razavi, "A study of injection locking and pulling in oscillators," IEEE, J. Solid-. State Circuits, vol.39, no.9, pp. 1415-1424, Sept. 2004.
[72] S.-L. Jang, C.-W. Chang, C.-F. Lee, and J.-F. Huang,”Divide-by-3 LC injection locked frequency divider implemented with 3D inductors,” IEICE Trans. Electronics., Vol.E91-C,No.6,pp.956-962,Jun. 2008.
[73] K.K. Hung, P. K. Ko, and C. Hu,” A unified model for the flickernnoise in metal-oxide-semiconductor field-effect transistors.,” IEEE Trans Electron Dev. 37:654–64, 1990.
[74] B. Razavi, “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol. 31, no. 3, pp. 331–343, Mar. 1996.
[75] H.-F. Teng, S. -L. Jang, and M. –H. Juang, "Modeling of degradation effects on the high frequency noise of metal-oxide field-effect transistors (MOSFETs)," Jap. J. Applied Physics, Vol. 44, pp38-43 2005.