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研究生: 許梵豪
Fan-Hau Hsu
論文名稱: 嵌入式IC標誌檢測系統設計與實現
The Design and Implementation of an Embedded IC Marking Inspection System
指導教授: 沈中安
Chung-An Shen
口試委員: 阮聖彰
Shanq-Jang Ruan
林昌鴻
Chang-Hong Lin
林淵翔
Yuan-Hsiang Lin
學位類別: 碩士
Master
系所名稱: 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 英文
論文頁數: 41
中文關鍵詞: 嵌入式系統IC檢測系統定位演算法模板匹配演算法
外文關鍵詞: Embedded system, IC marking inspection system, Positioning, Template matching
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  • 隨著科技的進步,越來越多的嵌入式裝置被應用在許多的工廠當中。其中,嵌入式系統有著低成本、體積小與低耗電等特性。由此可見,嵌入式系統有非常大的優勢能夠取代體積大且高耗能的工業電腦。而檢測系統在半導體工廠中扮演著非常重要的角色。它用來保證產品的品質與正確性,但由於檢測系統具有龐大的影像處理運算,因此,在嵌入式處理器上演算法複雜度變得非常重要。
    本碩士論文提出一嵌入式多核心之即時自動IC標誌檢測系統。其中我們將在本論文呈現基於嵌入式多核心處理器架構之IC檢測平台的系統層級設計與實現。此外,我們還提出了高效能的角度估計演算法用來進行目標IC的定位與方位旋轉角度。另外,我們所提出的角度估計演算法能夠有效的搭配經典的模板匹配演算法,進而大幅度的增加IC標誌檢測的準確度與執行速度。最後,我們更針對處理器架構來進行演算法層級的效能優化。在使用NEON單指令流多資料流和多核心技術下,系統能夠以更高的效率執行IC檢測,使能夠應用在目前許多的工廠中。經由實驗的證明,我們所提出的演算法能夠在嵌入式架構下能夠以高效率的執行能力進行運算,並且達到即時性。當目標圖像大小為640×480、模板圖像大小為80×100時,平均每張影像的IC標誌檢測可以在31微秒的時間以合理的準確度有效率的分辨出優良IC與瑕疵IC。


    This thesis presents the system architecture and the algorithm of a real-time automated IC marking inspection system based on an embedded multi-core platform. To be specific, the system-level design and implementation of an IC marking inspection platform with the embedded multi-core processors is illustrated. Furthermore, an efficient angle estimation algorithm is proposed such that a rotation and location of the IC chip can be identified efficiently. Moreover, the proposed angle estimation algorithm is combined with the classic template matching algorithm to accurately inspect the marking of the targeted IC chips. In addition, we present the algorithmic optimizations based on the architecture of multi-core embedded processors and the NEON general-purpose single instruction multiple data (SIMD) engine such that the computation time is significantly reduced. A formal outline of the proposed algorithm will be given and experiment results with PC-based platform and embedded-based platform will be presented showing that, comparing with traditional IC marking inspection algorithm, our proposed algorithm can be greatly improve image processing efficiency on embedded system platform. When the size of the target image is 640×480 pixels and size of the template image is 80×100, the average inspection time of our algorithm is 31 ms. And our algorithm can distinguish good IC chips from not good IC chips with reasonable accuracy.

    摘要 I Abstract II 致謝 / Acknowledgement III Catalog IV Figures VI Table VII I. Introduction 1 1.1 Embedded Based IC Marking Inspection System 1 1.2 The Features of This Work 3 1.3 Chapter Arrangement 4 II. Background 5 2.1 Automated IC Marking Inspection System 5 2.2 Template Matching 6 2.3 Single Instruction Multiple Data (SIMD) 7 2.4 Multi-Core Architecture 8 III. Proposed System Architecture Design for the ARM Processors 10 3.1 The Overview of the System Architecture Design 10 3.2 The System Hardware Architecture 10 3.2 The System Software Architecture 11 IV. Proposed IC Marking Inspection Algorithm 15 4.1 The Overview of the Proposed IC Marking Inspection Algorithm 15 4.2 Offline Phase – Learning of the IC Chip 16 4.3 Online Phase – Preprocessing 17 4.4 Online Phase – Angle Estimation of the IC Chip 18 4.5 Online Phase – IC Marking Comparison 22 4.6 Algorithmic Optimizations 25 V. Experimental Result 27 5.1 The Overview of the Experimental Results 27 5.2 Environment Setup 28 5.3 Video Capture and Display Performance Test 30 5.4 Test Speed Tests for the IC Marking Inspection Algorithm 32 5.5 Speed Tests for NEON and Multi-Core Optimization 36 VI. Conclusion 38 References 39

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