研究生: |
王暐綸 Wei-lun Wang |
---|---|
論文名稱: |
以真空蒸鍍即時量測法探討有機薄膜電晶體之遲滯現象 In-Situ Real Time Probing Hysteresis Phenomena of the Organic Thin-Film Transistors |
指導教授: |
李志堅
Chih-Chien Lee |
口試委員: |
劉舜維
Shun-Wei Liu 徐世祥 Shih-Hsiang Hsu 范慶麟 Ching-Lin Fan |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電子工程系 Department of Electronic and Computer Engineering |
論文出版年: | 2013 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 84 |
中文關鍵詞: | 即時量測法 、五環素 、銅酞菁 、有機薄膜電晶體 、遲滯現象 |
外文關鍵詞: | In-situ, pentacene, CuPc, OTFTs, hysteresis phenomena |
相關次數: | 點閱:364 下載:8 |
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本論文利用正型(P-type)非極性材料五環素(Pentacene)以及正型極性材料銅酞菁(Cooper Phthalocyanine, CuPc)作為有機薄膜電晶體(Organic Thin-Film Transistor)元件的半導體主動層,再以真空蒸鍍即時量測系統(In-situ real time measurement system),分別以三個不同蒸鍍速率(0.01 nm/s, 0.03 nm/s, 0.1nm/s)蒸鍍五環素薄膜電晶體,另外以不同外加電場(0V, 4V, 8V) 蒸鍍銅酞菁薄膜電晶體,觀察不同蒸鍍條件對有機膜層所造成的影響,並進一步探討五環素元件在不同的氣體環境(Vacuum, N2, Air)下所產生的遲滯現象。
在五環素的部分,我們發現以鍍率0.03 nm/s蒸鍍五環素元件,相較於其他鍍率,在三種氣體環境下所產生的遲滯現象皆最不顯著,並利用原子力顯微鏡觀察到以鍍率0.03 nm/s蒸鍍的五環素有機膜層,成膜性較佳且膜層缺陷較少,如此一來,載子捕捉(Carrier trapping)的情況較少,進而造成遲滯現象的縮減。
在銅酞菁的部分,由於銅酞菁為極性材料,故我們變化電場以期改變有機膜層覆蓋程度,我們發現外加電場對於有機膜層的覆蓋率有影響,當外加4V電壓時遲滯現象有顯著縮減,推測是電場可以令材料的排列更加一致。
另外,觀察三種氣體環境下五環素元件遲滯現象的變化,可以確定此一遲滯現象並非元件本身的特性,然而,此現象為一可逆的現象,當重新到達高真空度時,元件特性亦重新恢復。
總結以上實驗,我們可以知道無論是極性材料或非極性材料,我們都可以藉由改變蒸鍍速率或者變化外加電場來改變有機膜層的排列,並且最佳化蒸鍍條件。另一方面,將五環素元件暴露於不同的氣體環境之下,所產生不同程度的遲滯現象,讓我們可藉由薄膜電晶體蒸鍍不同的有機膜層,作為可重複利用的氣體感測器(Gas sensors)。
In this thesis, we report an in situ and real-time measurement method for the electrical characteristic evolution of p-type (Cooper Phthalocyanine, CuPc) and p-type (Pentacene) organic thin film transistors (OTFTs) during the deposition of organic thin film.
In the first part, We analyzed the thickness dependence of OTFTs where the different deposition rate (0.01, 0.03 and 0.1 nm/s) to grow the pentacene thin film on the bottom contact substrate at room temperature. We demonstrate that the carrier transport in pentacene TFTs is strongly affected by the quality of surface coverage in the first few monolayers. In addition, at our optimum deposition rate of 0.03 nm/s, we obtained a hole mobility of 0.27 cm2/Vs which is better than the slower (0.01 nm/s) and faster (0.1 nm/s) deposition rates. We speculate that this improvement of hole mobility is due to the increased surface coverage on the insulator, resulting in improved probability of charge percolation in the channel.
In the second part, We observed the growth of the CuPc TFTs with the different extra electric field (0V, 4V and 8V), and the substrate at 120℃. We found that the surface coverage of the CuPc thin film with 4V extra voltage is much better other extra electric field(0V and 8V), and hysteresis phenomena is unapparent.
In the last part, we measured the pentacene TFTs in different conditions and calculated the area density of the trapped electrons, found obvious hysteresis phenomena of pentacene TFTs in ambient air. Furthermore, the hysteresis phenomena were reversible in this studies, it would be an important factor to OTFTs as sensor.
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