本文提出了一種應用於頻帶內全雙工無線通訊系統中的獨立成分分析演算法的高吞吐量且高度可調適的預處理器。具體而言，本文提出了一種高性能矩陣乘法陣列。提出的矩陣乘法陣列架構是基於分時多工的處理方式所設計，從而大幅提高了硬體使用率。此外，提出的預處理器所使用的新處理流程被高度優化，使得置中運算、共變異數矩陣的運算以及特徵值分解能夠以平行化和管線化的方式進行處理。因此，使提出的處理器之吞吐量最大化，同時所需要的硬體元件數量可以最小化。提出的獨立成分分析之預處理器是利用電路設計流程所設計和實現。基於佈局後的評估進行性能上的估計。在本文中表明，提出的預處理器以約73.3k個邏輯閘的複雜度實現每秒40.69k個矩陣的吞吐量。與先前的文獻相比，所提出的預處理器實現了最高的吞吐量並且有最好的效率。

This paper presents a high-throughput and highly efficient configurable preprocessor for the independent component analysis (ICA) algorithm in in-band full-duplex (IBFD) wireless communication systems. To be specific, a high performance matrix multiplication array (MMA) is presented in this paper. The proposed MMA architecture is designed based on a time-multiplexed processing manner so that the efficiency for hardware utilization is greatly enhanced. Furthermore, the novel processing flow of the proposed preprocessor is highly optimized so that the operations and centering, the calculation of covariance matrix, and the eigenvalue decomposition (EVD) are conducted in parallel and in a pipelined fashion. Thus the processing throughput is maximized while the required number of hardware elements can be minimized. The proposed ICA preprocessor is designed and implemented with circuit design flow. The performance estimations based on the post-layout evaluations. It is shown in this paper the proposed preprocessor achieves a throughput of 40.7 KMatrices per second at the complexity of equal to 73.3 kGE. Compare with prior arts, the proposed preprocessor achieves highest processing throughput and best efficiency.

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