工作週期校正電路(Duty Cycle Corrector、簡稱DCC)的功能主要在於將訊號的工作週期調整到50%，廣泛地使用在雙倍資料速度同步動態隨機存取記憶體(double data rate SDRAM、簡稱DDR SDRAM)，雙取樣類比至數位轉換器(Double-Sampling ADC)，延遲鎖定迴路(delay locked loop、簡稱DLL)與鎖相迴路(phase locked loop、簡稱PLL)等需要在時脈訊號的上升緣與下降緣同時運作的電路，其效能之優劣往往取決於參考時脈正負半週之對稱程度，工作週期校正電路之重要性不言可喻。
工作週期校正電路在設計上可分為數位式與類比式兩種架構。數位式架構又可分為回授型與非回授型兩種，可以達到快速鎖定，但其精準度較差。類比式架構通常為回授型，以較長的鎖定時間來獲得較精準的工作週期校正。
本論文將提出一個架構極為簡單之類比負回授工作週期校正電路，利用脈波縮減/擴增延遲線來調整輸入訊號的脈波寬度使輸出訊號達到50%的工作週期，經由TSMC 0.18μm 標準CMOS製程來實現測試晶片，其面積只有0.18 × 0.14 mm2。經實驗證明，該電路具有20%~80%寬廣的輸入工作週期範圍、100MHz~1.4GHz超高動態輸入頻率操作範圍與-0.56%∼0.6%相當小之工作週期校正誤差。此晶片在1GHz操作頻率下之功率消耗只有1 mW，而峰值對峰值輸出抖動在1.4GHz下也僅僅達9.3ps，效能優異，非常適合低功耗、低抖動且極為廉價之應用。

The Duty cycle correctors (DCCs) are widely used to adjust the clock duty cycle to 50% for DDR (double data rate)-SDRAM, Double-Sampling ADC, DLL (delay locked loop) and PLL (phase locked loop) where both clock rising and falling edges are used for operation since clock signals with 50% duty cycle are extremely important for high-performance IC or system designs.
The implementations of DCCs are divided into two categories in literature: the digital and the analog structures. The realization of digital-structure DCCs is further categorized as feedback type and nonfeedback type. Both own fast locking speed ate the expense of relatively poor accuracy. The analog-structure DCCs are usually implemented as feedback type to get better accuracy with relatively long locking time.
In this thesis, an analog feedback duty cycle corrector with an extremely simple structure will be presented. The pulse width of the input clock is properly shrunk or stretched by a pulse shrinking/stretching delay line to ensure 50% duty cycle for the output signal. The proposed DCC has been implemented in a TSMC 0.18μm CMOS digital process. An input duty cycle range of 20%~80% is achieved. The duty cycle error is between -0.56% to +6% for the widest dynamic frequency operation range of 100MHz~1.4GHz. The chip area is merely 0.18 × 0.14 mm2. The power consumption is 1mW at 1GHz and the peak-to-peak output jitter is measured to be 9.3ps @ 1.4 GHz only.

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