在傳統頻率合成器架構之Charge pump phase lock loop(CPPLL)電路，因其相位頻率偵測器(PFD)之靜態相位誤差以及充電汞電流不匹配，將造成參考頻率突波。本文使用降低靜態相位誤差技術，防止頻率合成器在靜態相位誤差產生時對迴路充放電之機制，並搭配頻率校正系統以降低震盪器之增益(Kvco)與達到抑制雜訊以及參考頻率突波之效果。

兩個晶片設計使用TSMC 0.18um 1.8V製程完成，在晶片一主要是使用快速數位校正技術以降低震盪器增益且相對降低相位雜訊及參考信號突波，並利用降低電流不匹配技術之充電汞以降低電流不匹配所產生之參考信號突波。使用快速校正技術之優點為校正時間較短，並搭配具Op Amp負回授之充電汞達成降低電流不匹配之優點，但晶片功耗較大，使用快速校正技術測試參考頻率突波為-52.5 dBc，數位電路供應在1.8V，頻率合成器在1MHz的相位雜訊為-114.82 dBc/Hz，功率消耗為20.1mW，晶片面積為0.83 mm2。

在晶片二主要是設計一個在鎖相迴路中，因頻率偵測器之靜態相位誤差，以及充電汞電流不匹配，而造成參考頻率突波，因此使用輔助充電幫浦(AUXCP)技術做為補償機制，設計上主要是利用TDC偵測相位誤差，並利用輔助充電幫浦注入反向電流以降低電流不匹配現象且加入數位校正迴路以達到降低Kvco又可增加諧調範圍，且使用SAR logic數位校正降低功耗以及增加較正準確度，利用這些優點降低參考頻率突波。量測結果顯示頻率鎖定於5.0GHz時，距離主頻10KHz至100KHz的相位雜訊低於-60 dBc/Hz，而距離主頻1MHz處的相位雜訊為-113.23 dBc/Hz測試參考頻率突波為-58.57 dBc，晶片面積包含pad為1.11mm2。總消耗功率為22.8mW。

In the traditional charge pump circuit of phase locked loop (CPPLL), the reference spur is caused by static phase error of the phase frequency detector (PFD) and current mismatch by charge pump. This thesis will use the technology of reducing static phase error, preventing to charge and discharge on the loop when static phase error generated. It also matches with the frequency calibration system to reduce Kvco of an oscillator, so as to reduce phase noise and reference spur.

These two chips are fabricated by TSMC 0.18um 1.8V process. In the Chip 1 of this thesis, the digital calibration technology is used to reduce Kvco of an oscillator and phase noise as well as reference spur, and the technology of reducing current mismatch of charge pump is utilized to reduce reference spur generated from current mismatch. The advantage of using fast calibration technology is its short calibration time but it results in more power consumption. It matches with a negative feedback Op Amp of charge pump to reduce current mismatch. When the circuit is supplied with 1.8V, the measurement results are: reference spur is -52.5 dBc, phase noise of the frequency synthesizer at 1MHz is-114.82dBc/Hz, power consumption is 20.1mW, and chip area is 0.83 mm2.

In the Chip 2, reference spur will be caused due to static phase error of the frequency detector and mismatch of the charge pump in the phase lock loop, while Chip 2 uses AUXCP technology as compensation mechanism. In the design, it mainly utilizes TDC detection phase error, uses AUXCP to input reversed current to reduce current mismatch, adds digital calibration loop to reduce Kvco and add tuning range, wherein the digital calibration circuit uses SAR logic circuit to reduce power consumption and improve precision of calibration as well as reduce reference spur via these above methods. The final measurement results show that when frequency is locked at 5.0GHz, phase noise at 10KHz~100KHz is lower than -60 dBc/Hz, phase noise of the frequency synthesizer at 1MHz is-113.23dBc/Hz, reference spur is -58.57 dBc, chip area is 1.11mm2, and total power consumption is 22.8mW.

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