由於有良好的可擴充性、低功耗及出色的隨機存取表現，快閃記憶體在消費性電子產品中佔主要的地位，像是筆記型電腦和數位音響播放器等產品。快閃記憶體細胞的儲存資訊方法是將電子儲存於浮閘中，隨著製程的進步，使得每個細胞不再是單階儲存細胞 (Single-Level Cell, SLC) ，而是發展出多階儲存細胞 (Multiple-Level Cell, MLC)，因此每個細胞可以儲存1個位元以上的資料，但這也促使每個臨界偏壓的雜訊邊限縮小，因此製程越小就會讓快閃記憶體的可靠度和耐久度下降。為了解決這些問題，常見的方法為使用錯誤更正碼技術來解決快閃記憶體中的故障，其中故障又主要分為永久性故障和干擾性故障，然而當一個編碼字的故障細胞數量超出更正碼的修正能力範圍時，該編碼字就無法被修復。
因此，本研究提出錯誤遮罩技術來解決這些問題，核心概念為根據故障特性來儲存資料，以永久性故障來說，固定於邏輯1的錯誤雖然不能儲存邏輯0，但能儲存邏輯1，反之亦然。本研究提出兩種錯誤遮罩技術，一種是以資料反轉技術來遮罩故障，此外為了提升遮罩效益亦將其結合錯誤分散技術；另一種則是以位址重映射技術來遮罩故障，包括頁字位址重映射技術和站細胞位址重映射技術，此外根據干擾故障特性，該故障亦適用於上述的方法，在此篇將干擾故障視為虛擬固定型故障，並將其和永久性故障分為能儲存邏輯1的種類和能儲存邏輯0的種類，根據此種歸納方式，當資料寫入緩衝器時，適時地做資料或位址上的處理，以達到錯誤遮罩的效果。
本研究實現錯誤遮罩技術的硬體電路，包括資料反轉器、位址重映射器等，並發展一個模擬器以評估修復率以及良率，此外分析計算可靠度及硬體成本。根據實驗的結果，本篇所提出技術硬體成本只有1.1%，幾乎可以忽略，而且結合錯誤遮罩的技術修復率比只使用漢明更正碼技術提升約15%，良率最少也有93.4%，此外當使用時間達到300,000小時後，可靠度仍有98% 的水準。

Owing to the good scalability, low power consumption and excellent random access performance, flash memories are widely used in consumer products such as laptop computers, digital audio players and so on. The way to store information for a flash memory cell is by storing electrons into its floating gate. In spite of the conventional single-level cell (SLC), there are also the multiple-level cells (MLC) and the triple-level cells (TLC). However, the noise margin on each Vth level of the multiple-level cells shrinks significantly. Therefore, the aggressive scaling trend causes serious reliability and endurance degradation. In order to deal with this issue, the most popularly used technique is error correction code (ECC). In general, faults can be classified into two categories: the permanent fault and the disturb fault. However, a codeword cannot be corrected successfully if the number of faulty bits within a codeword is greater than the protection capability of the adopted ECC techniques.
Therefore, this thesis proposes fault masking techniques to solve this problem. The main idea is to store the safe data bits based on the characteristics of faults. For example, faulty cell with the permanent stuck-at 1 cannot store logic 0. That is, logic 1 is a safe value for this cell. There are two types of fault masking techniques. The first one is the data inversion technique. In order to enhance the masking probability, the basic data inversion technique can also incorporate with the fault redistribution technique. It masks faults by the address remapping techniques which including the page word address remapping and the bank cell address remapping techniques. Moreover, the disturb faults also can also be masked by the techniques mentioned above. In this thesis, we treat the disturb faults as the virtual stuck-at faults. We then group disturb faults and permanent faults into two categories. The first categories can store logic 1 correctly. Alternately, the second one can store logic 0 safely. Based on this observation, we can change the mapping of data or address bits before entering the page buffer for masking faults.
The hardware architecture for implementing the proposed fault masking technique includes the data inverter and the address remapper, etc. A simulator has been developed to evaluate the repair rate and the effective yield. Moreover, we also analyze and evaluate the hardware overhead and reliability. According to experimental results, the hardware overhead of proposed technique is about 1.6%. The repair rate of proposed technique is 15% higher than merely using the ECC technique. The achieved effective yield is more than 93.4%. Furthermore, the reliability of a flash memory can achieve up to 98% after 300,000 hours of normal operations.

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