研究生: |
王柏超 Bo-Chao Wang |
---|---|
論文名稱: |
以FPGA實現即時瞳孔偵測系統 A Real-Time Pupils Detection System Implemented on FPGA |
指導教授: |
王乃堅
Nai-Jian Wang |
口試委員: |
郭景明
Jing-Ming Guo 鍾順平 Shun-Ping Chung 呂學坤 Shyue-Kung Lu 方劭云 Shao-Yun Fang |
學位類別: |
碩士 Master |
系所名稱: |
電資學院 - 電機工程系 Department of Electrical Engineering |
論文出版年: | 2016 |
畢業學年度: | 104 |
語文別: | 中文 |
論文頁數: | 69 |
中文關鍵詞: | 人臉偵測 、瞳孔偵測 、快速連通標記法 、Real-time 、FPGA |
外文關鍵詞: | Face detection, Pupils detection, Fast connected-component labeling, Real-time, FPGA |
相關次數: | 點閱:369 下載:11 |
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交通安全一直以來都是人們所關心的話題,本論文即時瞳孔偵測系統為一個駕駛警示系統,透過影像處理的方式,從攝影機擷取影像進行瞳孔偵測,並且根據偵測結果進一步分析使用者雙眼的開闔狀態,經由開闔狀態判別使用者是否為瞌睡狀態,並且適時的以蜂鳴器給予警示。
本論文提出一個以純硬體的數位電路來實現即時瞳孔偵測系統,以人臉偵測為基礎,進而發展出瞳孔偵測系統,最後應用於瞌睡警示系統,此系統分為兩大部分:(1)軟體端的前置作業,(2)硬體端的實際運作。軟體端的前置作業主要為以機器學習(Machine Learning)的方式產生硬體端在進行人臉驗證所需要的分類器,主要分為三個步驟: (1)人臉特徵提取,(2)弱學習演算法,(3)Adaboost演算法。在硬體端的實際運作主要分為五個步驟:(1)人臉候選區截取,(2)人臉驗證,(3)瞳孔候選區截取,(4)瞳孔偵測,(5)行為分析,將這些步驟以模組化方式設計成硬體電路,此系統使用Verilog硬體描述語言(Hardware Description Language)以純硬體的方式設計,最後實現在Terasic DE2-115多媒體開發平台上。
實驗結果顯示此系統使用了個87,708個邏輯元件(logic elements),共佔用了Terasic DE2-115的76%,系統偵測率為86%,且處理速度為每秒達30張影像(NTSC Input)。
Traffic safety has been an important issue for most people. In this thesis, a real-time pupils detection system is applied to drowsiness alert system to improve the driving safety. Through image processing, pupils detection system can detect user’s pupils from the input image by camera and further analyze user’s eyes status. According to analysis results, the system can judge whether the user is in the state of drowsiness or not and provide the warning buzzer for the people who fall asleep.
In this thesis, we proposed a real-time pupils detection system based on hardware design. This research is on the basis of face detection to develop a pupils detection system, and apply to drowsiness alert system. This system is divided into two parts: (1)Off-line work based on PC software environment, (2)Real-time processing based on FPGA hardware architecture. The classifier needed for face examination on the FPGA is produced using the PC-based Machine Learning. There are three basic steps in machine learning: (1)Haar-like Features Extraction, (2)Weak Learning Algorithm, (3)Adaboost Algorithm. There are five basic steps in real-time processing: (1)Face Candidate Extraction, (2)Face Examination, (3)Pupils Candidate Extraction, (4)Pupils Detection, (5)Eyes Behavior Analysis. Each step is designed and modularized with Verilog HDL. It is implemented with Terasic DE2-115 development board. The experimental results show that the system costs 87,708 logic elements, which is about 76% of total logic elements of DE2-115. The system detection rate is 86% and the processing speed can reach 30FPS.
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URL:http://www.terasic.com.tw/
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URL:http://pro.sony.com/bbsc/ssr/product-EVID70P/