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研究生： 白聖輝
SHENB-HUEY BAY
論文名稱： 里德所羅門碼架構研究及電路設計
Reed Solomon code architecture research and circuit design
指導教授： 邱炳樟
Bin-Chang Chieu
口試委員: 徐敬文
Ching-Wen Hsue
黃忠偉
Jong-Woei Whang　
學位類別： 碩士
Master
系所名稱： 電資學院 - 電子工程系
Department of Electronic and Computer Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 中文
論文頁數： 59
中文關鍵詞： 里德所羅門碼
外文關鍵詞： Reed Solomon code
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    • 在通道編碼技術中，里德所羅門碼算是最常用且效率不錯的錯誤更正碼，舉凡在網路、數位電視、光碟片及手機等都有其運用，本論文主要是針對里德所羅門碼的主體架區分為四個區塊：(1)Syndrome的運算(2)找出錯誤位置(3)找出錯誤值(4)對接收信號的錯誤更正，分別對這四個區塊進行架構研究及提出改進的方法．本研究是由最基本的(7,3)碼，經由不斷的測試，最後往上擴升到(15,9)碼，在撰寫語言方面是在Xilinx的平台上以Verilog hardware description language來進行程式的撰寫及Debug，在透過modelsim進行各種波形驗證及synplify的電路合成結果，並與理論上的架構交叉比對，透過不斷的比對及測試，使整體的電路架構能達到最佳化，最後將其架構在FPGA上所呈現的整體效能進行列表及評估．根據本論文的研究結果及其演算法可將里德所羅門碼不斷往上擴升，仍可達到降低硬體複雜度及提升效能上的重要參考.

    Reed Solomon code can is an important channel coding technology which can be used to Correct the incorrect receiving signal with good efficiency , we can find its application in the field of the network , Digital TVs , CD , cell-phones .The thesis is mainly divided into four blocks namely (1) find out the syndrome (2) find out the error position (3) Find out the error value (4) Correct the error of receiving signal .Aiming to improve the performance of the above mentioned four blocks . A paper structure research is proposed .we have thus implemented the (15 , 9 ) code ; it is written and debugged by Verilog hardware description language on the platform of Xilinx , and verified the wave form by the Modelsim software and synthesis the result of circuit by the Synplify software ,Let the structure of the whole circuit reach the optimization by comparing and testing constantly.
    Finally , the results of this thesis show that the complexity of the hardware is reduced and the speed of operation is improved efficiently based on the FPGA structure, which is an improvement of the relative studies.

    目 錄 中文摘要 ----------------------------------------------------------Ⅰ 英文摘要 ----------------------------------------------------------Ⅱ 誌 謝 ----------------------------------------------------------Ⅲ 圖表索引 ----------------------------------------------------------IV 第一章 緒論 -------------------------------------------------1 1.1 簡介 -------------------------------------------------1 1.2 研究動機 ---------------------------------------------1 1.3 Reed Solomon code架構研討及電路設計 ------------------2 第二章 里德所羅門碼理論原理 ---------------------------------4 2.1 有限場的概念 -----------------------------------------4 2.2 有限場GF 內的元素 ---------------------------------5 2.3 里德所羅門碼編碼 -------------------------------------6 2.4 里德所羅門碼解碼 -------------------------------------8 第三章 里德所羅門碼編碼架構 ---------------------------------12 3.1 里德所羅門碼編碼架構設計 -----------------------------12 3.2 里德所羅門碼編碼架構設計流程 -------------------------12 第四章 里德所羅門碼解碼設計 ---------------------------------15 第五章 里德所羅門碼解碼RTL分析及硬體電路設計 ---------------18 5.1 有限場乘法器 -----------------------------------------18 5.1.1 有限場乘法器基本理論 ---------------------------------18 5.1.2 驗證 -------------------------------------------------21 5.1.3 RTL Level --------------------------------------------21 5.1.4 Gate Level -------------------------------------------22 5.2 里德所羅門碼Syndrome產生器 --------------------------23 5.2.1 里德所羅門碼Syndrome產生器設計架構 ------------------23 5.2.2 驗證 -------------------------------------------------23 5.2.3 RTL Level --------------------------------------------24 5.2.4 Gate Level -------------------------------------------24 5.3 Berlekamp Massey演算法 -----------------------------26 5.3.1 Berlekamp Massey演算法基本理論 ---------------------26 5.3.2 Berlekamp-Massey 演算法流程圖 ----------------------28 5.3.3 驗證 -------------------------------------------------30 5.3.4 RTL Level --------------------------------------------31 5.3.5 Gate Level -------------------------------------------32 5.4 有限場除法器 -----------------------------------------32 5.4.1 有限場除法器基本理論 ---------------------------------32 5.4.2 驗證 -------------------------------------------------35 5.4.3 RTL Level --------------------------------------------36 5.4.2 Gate Level -------------------------------------------36 5.5 錯誤位置 ---------------------------------------------37 5.5.1 尋找錯誤位置 -----------------------------------------38 5.5.2 驗證 -------------------------------------------------41 5.5.3 RTL Level --------------------------------------------42 5.5.4 Gate Level -------------------------------------------43 5.6 Forney演算法 ----------------------------------------44 5.6.1 Forney演算法理論架構 ---------------------------------44 5.6.2 Forney演算法設計流程圖 -------------------------------46 5.6.3 驗證 -------------------------------------------------47 5.6.4 RTL Level ---------------------------------------------48 5.6.5 Gate Level --------------------------------------------50 5.7 更正錯誤 ---------------------------------------------51 第七章 實驗平台 ---------------------------------------------54 7.1 硬體介面 ---------------------------------------------54 7.2 MAP FPGA ----------------------------------------------55 第入章 結論與未來展望----------------------------------------56 參考文獻 ----------------------------------------------------------57 作者簡介 ----------------------------------------------------------58 授 權 書 ----------------------------------------------------------59

    參考文獻

    [1] DR.BERNARD SKLAR,Digital Communications, Prentice Hall International Editions,New York,pp.436-460,1984.
    [2] I.S.Reed,M.T.Shin,T.K.Truong,VLSI design of inverse-free Berlekamp-Massey algorithm,IEEE Proceedings-E,Vol.138,No.5,SEPTEMBER 1991.
    [3] Adina Matache,Encoding/Decoding Reed Solomon Codes,Department of Electrical Engineering University of Washington,October 20 1996.
    [4] S.Lin and D.J.Costello,Jr.,Error Contro Coding,Prentice Hall,New Jersey 1982.
    [5] Azaleah Amina P.Chio,Jonathan A.Sahagun,and Delfin Jay M.Sabido IX,VLSI implementation of a Reed-Solomon error-correction codec,advanced Science and Technology Institute Department of Science and Technology,2002.
    [6] Hsie-Chia Chang,Chien-Ching Lin and Chen-Yi Lee,A Low-Power Reed-Solomon decoder for Stm-16 optical communications,Department of Electronics Engineering National Chiao Tung University Hsinchu,Taiwan,2002.
    [7] Lijun Gao and Keshab K.Parhi,Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec,Department of Electrical and Computer Engineering University of Minnesota,Minneapolis,MN 55455,USA,2001.
    [8] Dilip V.Sarwate and Naresh R.Shanbhag,High-speed Architectures for Reed-Solomon Decoders,IEEE Transactions on very large scale integration systems,Vol.9,NO.5,October,2001.
    [9] Hsie-Chia Chang and C.Bernard Shung,New serial Architecture for the Berlekamp-Massey Algorithm,IEEE Transactions on communications,Vol.47,NO.4,Appil,1999.
    [10] Chin-Liang Wang and Jyh-Huei Guo,New Systolic Arrays for C+AB2,inversion,and division in GF(2m),IEEE Transactions on communications,Vol.49,NO.10,October,2000.

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