With the adoption of vertical stacked structure and charge-trap cell design, 3D NAND flash memory decreases the cost-per-bit and becomes the mainstream in the storage market. Each cell in NAND flash memory can endure only limited write and erase operations, because every operation can cause the damage to NAND flash memory and increase the error bits. Since the bit errors are highly related to the data pattern, conventional works such as data randomization distribute the threshold voltage states uniformly to prevent the worse-case data pattern. However, data randomization may miss the opportunity to improve the SSD’s lifetime because the distribution of threshold voltage states is uniform whatever the access behavior. In 3D charge trap NAND flash, as the lower states would incur more right shifting than a cell with higher states, the access behavior may influence the bit errors. In this study, we propose a error mitigation scheme to improve NAND flash memory reliability by utilizing the characteristic of 3D charge trap NAND flash memory to encode the written data asymmetrically. Compared with related work, our proposed Nimble Mapping SSD could increase the reliability with less memory overhead. In the retention error, NMS has similar encoding effect and the experiment results show that the BER is averagely 1.2% lower than related work. Furthermore, NMS can decrease the BER of program variation by an average of 17.1%.

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