快取記憶體在微處理機效能中扮演著舉足輕重的角色，在本論文中我們設計與實現一個與ARM922T架構相容之快取記憶體系統(Cache System)智財(Intellectual Property, IP)，透過此快取記憶體系統可以有效的降低微處理機在處理資料時等待匯流排的時間。快取記憶體系統包含：8 K位元組指令快取記憶體、8 K位元組資料快取記憶體與寫出緩衝區，採用TAG-RAM架構設計可在最的時間內搜尋出資料，另外，使用AMBA匯流排協定可輕易的與其他智財連接，發展功能更加強大的微處理機。
目前我們已整合了Proto-ARM9M、快取記憶體系統、系統協同處理器與AMBA匯流排介面於Xilinx的Spartan-3 XC3S1500-4FG676 FPGA以及TSMC 0.18 μm元件庫上實現。FPGA設計驗證部分，共使用了12901個LUTs，最高操作頻率可達14 MHz，並於實驗板上搭配自行開發的測試環境以驗證所有測試程式及功能。元件庫方面，核心面積為2580.48 μm × 2586.06 μm，等效閘數(Gate Count)為382854閘，整體晶片面積為3250.92 μm × 3256.34 μm，在SS模式下操作頻率為50 MHz。

Cache is very important part in processor performance, in this thesis, a cache system compatible to ARM922T architecture and controlled by the Proto-ARM922 system coprocessor is proposed. Through this cache system, the bus access time for the processor is dramatically reduced when processing data. The cache system includes an 8K-Byte instruction cache, an 8K-Byte data cache and a write buffer. The cache system uses TAG-RAM and uses AMBA 2.0 bus to interface other IP so that it can develop more powerful micro-processor.
The resulting system has been implemented and verified with Xilinx Spartan-3 XC3S1500-4FG676 FPGA and TSMC 0.18 μm cell library. In the FPGA part, it takes 12901 LUTs and operates at the maximum working frequency of 14 MHz. In the cell-based part, the core occupies 2580.48 μm × 2586.06 μm, which is approximately equivalent to 382854 gates, and the whole chip occupies 3250.92 μm × 3256.34 μm, and in the SS (Slow NMOS Slow PMOS model) simulation condition it operates at the maximum working frequency of 50 MHz.

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